RocketIO evaluation

Jan 20, 2004 3 Replies
T

I was wondering if anyone has a reference design I could peak at. I just need something simple to demonstrate a working RocketIO with a XC2VP50 chip and the Virtex-II Pro FF1152 PROTO Board. As of right now, our design evaluates the gt_custom block and was configured using the architecture wizard. We have supplied the block with the five correct input clocks as specified (with REFCLK running and 50MHZ). We also set the parameter TXINHIBIT to high, which should cause TXP = 0 and TXN = 1, but both seem to be at ground.



Any help, suggestions or simple reference designs would be greatly appreciated.



Best Regards, T. Justin Campbell


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A

I just finished a small design which uses the Rocket IO as a transceiver only. I use the GT_ETHERNET macro for a 2 byte data path.the device is a V2P7 Are you getting the DCM (which i am assuming you are using to generate your clks) to lock ? simulation is tricky ..you have to provided the TXRESET and RXRESET after the DCM has locked. And u have to run the simulation for a good length of time before things settle down. I use Active HDL for my simulations and XST for synthesis. I can send you a copy of verilog file if you think it will be useful. let me know ...also it will be great if you can mention other issues u see with it, as I am also new to RIOs. good luck, adarsh

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A

sorry...i mean i use the rocket IO as receiver only

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H

If you are going to receive something, something else has to transmit it. The simplest transmitter you are going to find is probably on the board you already have.

You may have to build a loop-back connector.

Anyway, I suggest looking for a self-test setup rather than just something to test the receiver.

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