reset strategy FPGA Igloo

Hi Rick,

On 08/11/2013 15:47, rickman wrote: []

Between the I/O Bank and the FPGA core there's the BSR mandated by the IEEE-1149.1 standard (JTAG) that you can control during programming. I'm trying to look for 'default' values, but that is not essential since when both VCC and VCCI will be above the functional voltage level the I/O will first drive the input and 200ns later the output, resulting in the transition '1'->'0' on RST_p which, in turns, generates a transition '0'->'1' on RST_n, to be used internally as an active low reset.

Actually you do not need to have VCC functional *before* VCCI. I paste here an excerpt from the app note:

(pag.2)

HTH,

Al

Reply to
alb
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I hope all this is clear to you, it is not clear to me. But if it works, then great. There's your solution. Will you have to prove to someone that this will work in a real system by analyzing the vendor's documents? That might be a bit tough.

BTW, what is the fabric logic doing while all this Vcc ramping is going on. What does it do if the logic VCC ramps up before VCCI does? I guess if the I/Os are not enabled it doesn't matter much what it does if it gets a reset pulse before the outputs are enabled. Can you assure that?

--

Rick
Reply to
rickman

I do not get what is not clear for you, it might be I'm missing something.

Not more than proving that any other piece of the logic works. My system is relying on the internal PLL properly working and I only have the datasheet to consult. What else should i be considering?

The I/O are tristated until the *last* supply is powered. What the internal logic does before that point is kind of useless to speculate on since whichever state will end up with it will come back to a known one after reset.

Reply to
alb

There is language in the documents you have provided that is not clear. They talk about the boundary scan logic but don't explain how this impacts the start up operation.

But you *aren't* relying on the data sheet. You are relying on an app note that seems to have gaps from what I have seen. I just can't fully grasp how the chip is expected to operate. They have boundary scan logic which has to be reset on power up. Where does that reset come from? Does the boundary scan logic impact this reset strategy at all? Can you show this from the documentation?

The IOs are tristated, but what is going on with the inputs? This is all being explained piecemeal so I can't see the full picture to know that all of the timing works. Also realize that I read your post and try to remember what you have written. Then I don't think about this for days until the next post. So I don't remember all the details. If you have explained something a week ago I have long since forgotten it.

If you are happy, then it doesn't matter if I understand it. But from what you have said, there will be some sort of review of your approach. You need to be able to justify all this adequately for the review.

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Rick
Reply to
rickman

Hi Rick,

On 15/11/2013 08:20, rickman wrote: []

Well, it is possible that i misunderstood that part, but reading the app. note again it looks to me that when the I/O is *not* enabled (i.e. prior to both VCC and VCCIBx operational) the fabric logic is driven by the BSR register.

Since prior to both VCC and VCCIBx operational the I/O is tristated, I do not care much about what is going on internally since it is not going to affect the I/O.

OTOH when both VCC and VCCIBx are operational there's a sequence of 'activation' of the input first and the output secondly which provides the '0'->'1' condition for an active low reset labelled in the document as RST_n.

The BSR is normally 'reset' through the JTAG port (either synchronously or asynchronously), but does not really matter because when the JTAG is not active the chip drives output from its internal fabric and samples input transparently.

Nope, I'm trying to look for the JTAG implementation description of this device, but I'm having hard time to find it.

[]

I completely understand.

Yep!

Reply to
alb

I think in terms of pictures, so I probably wouldn't fully understand all of this until I saw a timing diagram. Nothing fancy, just something that shows all the events in a timeline along with the various signals in the reset chain. I suspect something like this would be good material for your review. I believe the events are like this...

Vcc _____------------ VccIO ________---------

--or--

Vcc ________--------- VccIO _____------------

-- results --

BSR drives internal logic, High = drives, Lo = not driving ---------________

Inputs enabled _________-------- Outputs enabled ____________----- Input to reset logic xxxxxxxxx---_____

The reset is your reset circuit for the rest of the chip.

Now that I see it in diagram form, I think you have it covered.

--

Rick
Reply to
rickman

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