Hi Rick,
On 08/11/2013 15:47, rickman wrote: []
Between the I/O Bank and the FPGA core there's the BSR mandated by the IEEE-1149.1 standard (JTAG) that you can control during programming. I'm trying to look for 'default' values, but that is not essential since when both VCC and VCCI will be above the functional voltage level the I/O will first drive the input and 200ns later the output, resulting in the transition '1'->'0' on RST_p which, in turns, generates a transition '0'->'1' on RST_n, to be used internally as an active low reset.
Actually you do not need to have VCC functional *before* VCCI. I paste here an excerpt from the app note:
(pag.2)
HTH,
Al