We always specify bare-board testing and warpage and tolerances, so we don't get bad boards. What we can get is expensive boards.
Zero annular ring seems to be OK on inners. That reduces capacitance.
5 or even 4 mil traces are usually standard price. I don't know why my guy used 6 on the board that I posted.We do email our board houses and often they answer!
We don't prototype actual products; just go for it.
There are a number of them, As I said, If you are using a CM, you will need to talk with them and find who they use and talk to them about their requirements.
So, you aren't using a good CM, as they aren't using a good board shop, or at least didn't give you their expected failure rates up front. Yes, there are loss factors for parts, but if they didn't give you those when you started to negotiate the contract when you indicated you will be supplying some of the parts, they aren't doing their job.
Yes, it may be "cheaper" to use a shop like that, but you pay for it in those sorts of costs.
Yes, some "customers" are not worth it.
That's because you're obnoxious.
Just trying to help. My mistake.
Stop being obnoxious and you'll get more help.
But not fom me.
Oh, are you the rick from SED? I should have noticed. Bye indeed.
Am 07.01.2023 um 18:49 schrieb snipped-for-privacy@gmail.com:
I've done a 324pin 0.8mm BGA recently.
My PCB fab is:
I used all standard parameters like 0.2mm holes, 0.4mm via diameters and
0.1mm trace width and spaces on a 6-layer board, GND at layers 2 and 5. Power planes are used on layer 3, as well as additional power and signal routing.All was manufactured perfectly fine and the board works as expected.
I was the schematics developer as well as the layouter.
There are some optimazations you can do if you do both. You can try to join several pwr pins to one via and then get the space for placing 0402 capacitors under the BGA. (Recommended is max. 2 BGA-pads to one via)
Using 0201 caps saves you from doing tricky via omitting. Using 0204 caps did't help in my case.
You can also ignore some I/Os for routing critical high speed nets.
There is lots of room for playing around optimizing and finally you can use all BGA-pads. I used Altium and partly it was a fun job as well as a mess with length matching.
Doing 0.8mm is an easy job IMHO, also have done some 1mm BGAs, then used
0.5mm via diameter. The advantage of using 2 tracks between 2 balls is not too big. A 1mm 196ball FPGA has the same size as a 324pin 0.8mm chip, 15x15mm.And now how to assemble a BGA pcb ? Look here:
PS: Xilinx recommends lots of caps in power distribution network however on the eval boards like SP701, AC701 and others these caps are placed centimeters away from the chip...
As long as the path between the bypass caps and the power balls is low inductance (i.e., minimal paths then vias to power polygons) and low DC impedance (i.e., power polygons covering the caps and the device itself), there's no problem being centimetres away. If I remember my numbers correctly, at 100 MHz a tenth of the wavelength will be about
5cm, so placing closer than that gives no benefits. Details can vary depending on your needs, of course - if you have a lot of hard high-power simultaneous switching at higher frequencies then you need to be much more careful with bypassing than if it is more spread out.ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.