UP/DOWN Counter

I've used that chip or one of it's cousins, but that was a long time ago.

I don't think you can get a simple TC out for the middle of the chip. If you are just counting up, you can brew your own with a 3 input AND gate using the TC in and the bottom two bits of the top chip. Mumble, I'm not sure of the polarity on the TC. It might take some inverters.

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Check MC14158 or possibly 74LS491 Might be time to get a PIC

=A0 =A0 ...Jim Thompson

=A0 | =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 |

Can't you just preset it to x'300' and count down or to x'C00' and count up. al

Try a 74190 or 74192 or 74196 decade counter

(I assume you mean a count of 10, since all of these are 4 bit counters.)

No. 10-BITs

...Jim Thompson

"Jim Thompson" schreef in bericht news: snipped-for-privacy@4ax.com...

As these are 4-bit counters you will need three of them. Each has its own TC so to get a TC for the whole counter, you need to *AND* the TCs. To limit the counter to 10 bits, you'll have to make your own TC for the two least significant bits of the most significant chip.

|\\ __ U/D-------+---| >O---| | | |/ | | Q0----+--|----------|& |o---+ | | | | | Q1--+-|--|----------|__| | | | | | __ | | | +-| | | | | |& |o-+ TC2 | | | +-|__| | | | | __ | | | | +----------| | | | | | |\\ | | | | | +------| >O---|& |o---+ | | |\\ |/ | | | __ +---| >O--------|__| +-| | |/ | | TC1------------------------------------|& |--- TC10BIT | | TC0------------------------------------|__| created by Andy´s ASCII-Circuit v1.24.140803 Beta

petrus bitbyter

Done! As usual the Analog Guy wings it successfully ;-)

...Jim Thompson

See...

Newsgroups: alt.binaries.schematics.electronic Subject: Re: UP/DOWN Counter - UD-CTR-10BIT-74HC191.pdf Message-ID:

For schematic and simulation results.

...Jim Thompson

Sorry - I missed the "three stages" when I saw your message in ABSE, and realized my error when I saw it again in SED.

can't you just ignore the two high bits ? or do the top two bits some other way?

I need to simulate what another designer will ultimately do at device-level. Counter must not over-run, top or bottom. (It's a tracking ADC.)

I have it cobbled together and running with existing digital (behavioral) parts in PSpice; so I can test my analog portions quickly.

...Jim Thompson

Is there an analog way to stabilize the outputs?

ah, I suppose you've already thought of this:

TC0 ---------------------------+- ___ TC1 ---------------------------|&)-- CE0 .---+- bit8 --+------+- | bit9 +-|------|&)---. | | | .->o-+- | | _ | | | `--+ | U/D -|-|-+----+ )1>-' | `------)1>o-----+ `--------+

TC0 and TC1 are TC from the low order chips ___ bit8,9 are D0 & D1 fron the high chip, and CE0 is clock enable on the low chip. or could you just clock it 4 times faster and ignore the low bits?___ then you'd just need to and the three TCs together and feed it to CE0

Can't you just preset it to x'300' and count down or to x'C00' and count up.

Just dont use the 11th and 12th bit unless care what their state is.

Bob