I am working with the ACEX 1K30 and I don't understand the structure of
> the IOE. The diagram clearly shows three FFs; data input, data output
> and output enable. The three FFs even have different types of
> connections to the routing. But in the text, they seem to be saying
> that there is only a single FF in the IOE.
>
> Is there really only one FF in the IOE so that it can be either input or
> output? Is the OE FF always in an LE rather than the IOE? Seems like
> this would make for some trouble getting the timing in tight
> situations.
>
Yeah - been there, done that - I had great fun making a 10KE do a 100MHz SDRAM interface meet timing, due to the single flipflop :-( Someone once described the 10KE datasheet to me as "less than totally transparent" or some such.
The other gotcha is the implication that there is an asynch preset on the FF - in the text it then describes that the P&R software will automatically put an invertor fore and aft of the FF and use the async reset input (that does exist). Making a bit of a hash of your tco as a a result :-(
I was not a happy bunny that day, and from that day forward have made a point of not looking at Altera's diagrams only reading the text...
Commiserations :-(
Martin