Quartus II tutorial vs the real world

I'm working with a Stratix EP1S40 evaluation baord, after going through the tutorial successfully (there is no mention of pin assignments in the tutorial, that would have been a nice touch i think), I tried a similar nios processor design from scratch to no avail.

What I've figured out is this: if I begin with the given tutorial files, delete everything on the block diagram, and make a minimal system, everything works great. If I make the exact same minimal system starting from a new project file, then it won't work. Obviously there is some setting already adjusted in the example tutorial file that is not mentioned in the tutorial, but I can't figure out what it is. Has anyone else experienced this?

When it does not work, here is what happens. After programming the fpga, it runs momentarily (I can configure the led's to a given state to verify, also the GERMS monitor spits out the correct system boot id) and then the board defaults back to its original demo configuration.

any advice on what I need to do to get a new project working would be greatly appreciated.

-P

Reply to
pjjones
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ITS NOT JUST ME!!!!!

THANK YOU FOR POSTING.

I too am having problems with the NIOS eval board. I too have worked the tutorials and I too have modified the tutorials as you. See the post NIOS and OCI.

My FAE did call me back. I'm doing other things but come Monday I'll be back on the eval board trying my darnest to get it to do real world stuff.

Keep ya all posted.

Jer

Reply to
Jerry

I've got the Cyclone eval board. The tutorial for this _does_ mention pin assignments, you've to run a Tcl script called assign_pins.tcl or something similar (it's on a different PC that's off at the minute).

Things kept mysteriously breaking when I'd run this script and I found the script contained a device assignment statement which switched the device from a Cyclone 1C12XXX to a Stratix device (can't remember exactly which one). I just removed the device assignment line to stop it changing the device after I'd set it when setting the project up.

It might be worth checking your pin assignment Tcl script to check that it's not doing the same to you.

Nial Stewart

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

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Reply to
Nial Stewart

Hi,

I believe what's missing here is the requirement (for these boards) to tri-state unused IO pins. This is a project setting that is turned on in the example designs (and probably in the tutorial design files). To do this with your new design (in Quartus 2/3.0):

Go to the Assignments menu --> Device --> Device & Pin Options -->

Unused Pins tab, and select the option to reserve all unused pins "As inputs, tri-stated".

Some background: The Nios dev boards have a feature for implementing and demonstrating remote reconfiguration of the Stratix/Cyclone device. This is implemented by a single IO which is connected to the board's MAX7128 configuration controller - if the FPGA asserts this IO, the MAX device will follow the power-on configuration sequence in an attempt to boot the FPGA with (presumably) a new FPGA configuration stored in flash. However, if this pin is not used in your design, and is not reserved as tri-stated, the pin could (and does) float to tell the MAX device to perform re-configuration.

Our literature on the older Nios/Apex dev board *did* have this step in the tutorial steps (although that board didn't have the "blow your brains out" remote reconfiguration feature, you did need to tri-state unused IOs to prevent bus contention if you weren't talking to external memory in your design). This step was regrettably omitted in the Stratix/Cyclone tutorials -- I will make sure this is corrected for the next rev of these documents!

Another documentation note: The 1S40 board manual document "mnl_nios_board_stratix_1s40.pdf", does have pin-out tables describing pin assignments for all features on the board. Alternatively, the "standard_32" example design for the 1S40 board has Quartus pin assignments for all features as well (this makes it very easy to just grab what you need for a new design without worrying about an incorrect IO assignment).

Also, to Jerry, who had OCI problems: I believe this is a different issue, as your design is booting/resetting just fine but the debugger wouldn't connect... if you have not heard from your FAE, feel free to zip up your Quartus project and send it my way to the 'decoded' email address below. My yahoo mail account has been completely hosed as a result of the M$ "patch" virus going around :(

Jesse Kempa Altera Corp. jkempa at altera dot com

Reply to
Jesse Kempa

Hmm. I've done several designs that I've tried on en NIOS Development kit.

Have you assigned the correct location to all the pins?

Pay attention to the PLD_RECONFIGREQ_N which will trigger a reconfiguration when asserted. If you download your code directly to the FPGA without storing it in the FLASH it will start running the design stored in the FLASH.

Petter

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Reply to
Petter Gustad

Make sure all unused pins are "As Inputs Tri-Stated". This is done in the Settings-> Device ->Device & Pin Options

I think having the default "As output, driving ground" causes problems on the development board, because some of the unused pins may be connected to other things such the recofiguration signal to the Max Device (active low).

I have burned myself plenty of times on this.

--Chris

Reply to
crob

Aye, this is explicitly mentioned in the tutorial (Cyclone).

Nial.

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

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Reply to
Nial Stewart

Thanks for all of the suggestions. My solution was to change the unused pins to be configured "as inputs, tri-stated". Once I made this change, my minimal test system started working. (Which unfortunately led to the conclusion that there are additional problems in my real project ... oh well, 1 down ?? to go)

I do wish the stratix tutorial at least *mentioned* this, even if it was something like, "The following settings have already been made for you in this tutorial: " with a bullet list following. That way, there would at least be an idea of where to begin searching when faced with an unknown problem.

Thanks again,

-P

Reply to
pjjones

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