Well, if you initialize the flip-flops through the bitmap you'll know that they'll wake-up in a given state. For example, in Verilog:
reg outgoing_rst = 1'b1;
You can use FPGA Editor to verify that the FF in question is set to the desired value in the bitfile.
This also applies to a counter you may want to use to time the assertion/de-assertion of the signal:
reg [11:0] rst_counter = 12'b0;
With this you know how that module will start from a fresh bitfile load. The remaining logic isn't very difficult and should be pretty reliable. For example, you could increment the counter with one of the clocks and stop incrementing when the MSB is "1". You'd use a case statement to fire off different events during the power-on reset cycle. You can even add a warm boot feature by having other logic reset the counter during operation.