Problem with LogicLock and register packing

Hi Peter,

This does occasionally happen when Quartus' register packing heuristics can't find a register packing that matches your back-annotated logic lock constraints, even though clearly a packing solution exists (since it was found on the first compile).

Three things to try:

1. Back-annotate this logic-lock region to the logic cell (rather than LAB) level. Generally it is best to back-annotate to the LAB level to give the compiler more flexibility. In this case though, by back-annotating to the logic cell level you will make the correct register packing very explicit (this LUT goes with that register), and that should make Quartus reproduce the register packing you need and get you a fit.

1. Upgrade to Quartus 4.1. I can't guarantee that will fix this, but it probably will, since we improved the handling of back-annotated designs with area-minimizing register packing in Quartus II 4.0 and

1. Send me the problem design ( snipped-for-privacy@altera.com). If you can send two Quartus archives -- one with the non-back-annotated design that fits, and one with the back-annotated one that doesn't fit -- that would be ideal. I'll get someone in my group to confirm that the problem does not exist in Quartus II 4.1 (or fix it if it does still exist).

Regards,

Vaughn Altera

Hi Vaughn,

Thanks for the reply.

I erroneously stated that I am using QII 3.0. I am actually using QII 4.0 SP1.19.

I will discuss further through email.

-- Pete