Many of the recent Microchip PIC power-on-resets use a digital counter internally. I'm guessing that they're working within confines similar to what you have and also they're trying to keep power consumption while asleep to a minimum and deal with brownout recovery. I don't know the details but they must be taking on-chip clock in the 10's or
100's of kHz to tick everything along.What requirements do you have regarding power consumption while asleep, brownout recovery, ?
Tim.
Why not just hold reset true as long as Vcc is below some level?
John
I need a power-on reset that lasts around 5ms.
Process is CMOS
Components available besides CMOS:
Lateral PNP Vertical PNP Caps up to 20pF Resistors up to 1Meg
Suggestions?
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |
I need to time-out long enough that a charge-pump has reached maximum.
Charge-pump is regulated by controlling input, has no load other than capacitance, so I can't sense CP voltage without disturbing things.
...Jim Thompson
This dude doesn't sleep, but power consumption is critical.
(Hearing-aid-related is all I can say right now.)
...Jim Thompson
tend to be inferior to parts
I think that battery-operated consumer single-chip gizmos were using a similar (although probably no band-gap) technique back into the early
80's. At least that was the only way I could figure they were generating a power-on-reset delay of hundreds of ms. Some of these worked down below 1.2V. I never did figure out what magic they used internally (maybe related to, or even exactly the same as, Jim's mention of an internal charge pump?)Tim.
tend to be inferior to parts
I think that battery-operated consumer single-chip gizmos were using a similar (although probably no band-gap) technique back into the early
80's. At least that was the only way I could figure they were generating a power-on-reset delay of hundreds of ms. Some of these worked down below 1.2V. I never did figure out what magic they used internally (maybe related to, or even exactly the same as, Jim's mention of an internal charge pump?)Tim.
There are a lot of parts built in CMOS that do this, but very little on how they do it internally. Here's one (first made by Microchip or perhaps some company they bought):
It's basically what you want, except with a 200ms delay.
In Microchips' block diagram they show a bandgap reference, a comparator and a delay circuit, just as you might expect.
Similar non-stand-alone functions that people have designed into chips tend to be inferior to parts such as the above. Hopefully you can do better!
Best regards, Spehro Pefhany
Even with a FET gate? Or is that a stupid question -- the closest I've been to IC design is that 4th-year class where you build an op-amp out of a CA3096 and a CA3086.
And to think I'm charging folks for my time today -- good thing it's something I already know how to do.
So you're back to an RC oscillator and a counter?
I don't want to sense the CP output voltage. It's driving a capacitive transducer, and sensing will load it..
...Jim Thompson
The highest voltage on-chip is the pump output, so a FET gate needs a drain supply.
...Jim Thompson
I'm contemplating a second pump with smaller capacitors as a counter... something like "CP-Style-Counter.pdf" on the S.E.D/Schematics page of my website.
Since it would be ratiometric with the main pump I can use a sensor that's below VDD and thus powerable.
...Jim Thompson
Your favorite oscillator and a 20 bit counter. In the meantime you can continue work on that cap multiplier. Cheers, Harry
50KHz relaxation osc, 8 bit counter, flip flop?
There was an experimental thread here last year on CMOS flip flops that indicated that they could be 'guided' into the required POR state by pull up/down R's. That could maybe be the way to bring up the counter and flip flop in the Reset state.
Hello Harry,
That is how I would do it, similar to a CD4060.
It may not need 20 bits. That would depend on the trade-off between die area per pF for the oscillator capacitor and the real estate each divider occupies. It also depends on how small a current can safely be generated and used to charge and discharge that cap. 20pF seems pretty fat for a chip.
Jim, maybe you can instead incorporate some nifty logic that holds down the reset until the charge pump has reached the desired voltage level, like x times battery level.
Regards, Joerg
Hello Jim,
I don't know the architecture. But is there a way to sense and switch the divider path hi-Z when done sensing?
Regards, Joerg
POR circuits are NOT trivial to design. Many people have crashed and burned using latches, 555 timers and other schemes. This is why Maxim can get 50 cents for a reset chip. I have been told by very smart people that the only valid approach to a POR circuit is a transistor- level approach. You have to have fully characterized transistor models if you expect to SPICE it, macromodels will not do. Be sure to exercise the circuit (reality preferred to SPICE) for very slow as well as very fast power turn-on and over a range of temperatures and loads. This is really a design challenge so don't take it lightly.
Absolutely not, that's why I was asking.
I'm at the device level.
I've found a solution I can't divulge at the moment, maybe in two years, that tracks process corners and times relative to what needs the reset.
...Jim Thompson
ROTFLMAO ;-)
...Jim Thompson
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