Pin Sort

I have found that I must take special care with CPLDs, especially the 7000s Altera that I worked with. They root a lot easier if I allowed the compiler/placer to choose the pins.

FPGAs I found much easier. I use a lot of Cyclone 1C3 and 1C6 QFP packages and I haven't found any problems with wayout layouts.

Victor Schutte

the 7000s

Another way to put this is never draw the schematic before you've done at least one pass on the CPLD code and fit it into the part. It's been a while since I've last done design with CPLD's but in the old days the big issue was routing signals between the blocks. If you can fit a design such that each block of I/O's has unused connections to the global routing pool, you'll be less likely to require pinout changes if you need to update the logic. I think newer parts have a little more flexibility such as programmable routing between the macrocells and the I/O's, and some "CPLDs" are just small FPGAs with instant load from flash. But I think its still a bad idea to design a CPLD into a board before designing the internals.

packages

I rarely have the luxury of designing FPGA internals before the board schematic. I usually design the FPGA guts while the board is in layout and fabrication. Usually I find no problems with pin assignments, but I have been burned when using some of the advanced I/O features of Virtex

1. In particular you need to watch out for differential signal pairing requirements and also IOB clock routing. When you use DDR flip-flops in these parts (and I imagine Spartan 3 is similar) pairs of IOB's share some clock routing resources making it impossible for example to use one IOB in a pair for the DQ of DDR SDRAM and its partner for a DQS. The shared routing resources use the same pairing as the differential I/O.

sort?

control

I'll use Xilinx CoolRunnerII. I have got Nuhorizons CoolRunnerII evolution board. I think CPLD is unnecessary. Because FPGA is same or cheap price, it can take more big program from CPLD and a lot of people use FPGA. Books tell about FPGA. Thank for your answer

people

When you make a price comparison between CPLD and FPGA make sure to include the configuration storage for the FPGA. These have come down in price lately, but can still represent a large portion of the total cost when using a small FPGA. Also remember that the CPLD comes up "hot" so it can handle things like processor reset, while an FPGA takes time to load. Also if you decide to load the FPGA from a processor to save the configuration memory cost, you can't also use it to implement processor reset.