Original (5V) Xilinx Spartan ?

I don't understand why this is so hard to understand. Nothing personal, it is just that a lot of people keep trying to make the comparator solution work. The problem is that the output of the comparator has the same problem as the output of FF1. It can be inderterminate (between logic 0 and logic 1) for an indeterminate amount of time. "meta" can be in transition at the time that FF2 is clocked with will clearly lead to FF2 going metastable.

-- Marc Baker Xilinx Applications (408) 879-5375

I accept that with op amps with non infinite gain then just at the edges of the comparator detection the comparator timing might be slow or unknown(what you have called metastable-I don't know why), this does not matter.

Lets just suppose that ff1 was only just metastable and was nearly high. In this scenario with meta unknown then, the mux on ff2 may be switching wildly or trying to average (I don't know modern semi theory) the two inputs to ff2. However ff1 is just about 1 and so is "not ff2" and ff2 will see a solid 1.

There may be a hole in my "design" but unless there is something about op amp comparators I have forgotten (I did the theory about 15 yrs ago) then this isn't it.

The problem with a forum like this is that someone steps out of the box and other people think that the "out of boxer" has no experience at all. As my last sentence sort of implied I'm not looking for a solution, the maths for metastability is well understood and I'm not looking to pay the obvious penalties for not using the classic solution.

There is an issue if FF1 is metastable on two successive clock edges when the input is slowly rising as FF2 will toggle twice, which simple design practice can solve, but there is no issue if FF1 is meta twice with an input pulse at exactly the clock period (FF2 toggling twice is what the input has done). Other than that I haven't understood you.