Ones Count 64 bit on Xilinx in VHDL

< Using 63bits rather than 64 bits takes precisely 63 adder cells>

Should say Using 63bits rather than 64 bits takes precisely 63-6 adder cells and

64 bits take 63.

Its been awhile. You probably didn't realize I was using 32x for oversampling

Reply to
JJ
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(snip)

Well, I might describe Peter's as using 12 bit wide (or is it deep) carry save adders. I forget by now if he actually made a tree out of it, though.

-- glen

Reply to
glen herrmannsfeldt

Here's a pipeline in Verilog - the theory should translate easily to VHDL. I'm a beginner at Verilog, so forgive me if there's something obviously wrong here.

module pop64( input clk, input [63:0] vec, output reg [6:0] sum);

reg [63:0] s1, s2, s3, s4, s5;

always @(posedge clk) begin s1

Reply to
Paul Marciano

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