there are async resets ... and async resets...
In all the designs at work async resets are used throughout... except, as has been pointed out, where the result of the flip flop can be guaranteed after a few clock cycles. Where few is a debatable number. There is a big BUT to this... if the clock is continuous, then the async reset actually comes from a reset synchroniser, that is the clock using the reset generates the reset. If the clock is gapped (e.g. SPI clock) then the reset is async. And yes... there is one reset per clock line.
My preference is to use the double latch system ... "rst_in" clears both latches and one latch cascades into the other.. shift register style... the result is the reset for that clock.
Simon