Hi,
On some pretty obvious piece of VHDL (below) QuartusII does not inferred any RAM !!!!!! (whatever "width" value is...)
Any help how to convince QII to use RAM and not LEs ??? (all ram options are set to ON... and I've seen it working well on other occasions so what Is wrong here ?)
many tks.
lc.
(I used QII7.0web ed.)
--snip--
type k_ram_type is array (0 to (2**width)-1) of std_logic_vector(17 downto 0); shared variable k_ram: k_ram_type;
begin
process(a_clk) begin if rising_edge(a_clk) then if en_A='1' then if wr_en_A='1' then data_A_out