Hi all,
I am working on a project that will translate VHDL to EDIF format, the netlist shall only contain logic gates. I have tried XILINX XST, but netlist not only have logic gates but also have LUT and cell such as multiplier. So I transfer to Synopsys, by using target library and_or , I could see the netlist have 'and' ,'or','inv', "ripper' primitive. I really need to find out description for and_or library. But searching the whole Synopsys folder, none of documentation is about library.
Anyone knows where can I find the library documentation?
Thanks in advance
Simin