Anyone use HDL as design tool for PCBs?

Hi, Does anyone out there in usenet-land know of tools to let you design Printed Circuit Boards with VHDL? I'm ready to switch from schematic entry, I want portability! (And all the other good reasons I switched from schematic entry for my FPGA designs) Anyone use a PCB layout tool that accepts EDIF files? I see there are translator tools. Anyone ready to share their experiences, pitfalls et cetera? thanks for reading, Syms.

Reply to
Symon
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Features like pin swapping, gate swapping and cross probing will only work with a tightly integrated pcb and "source" toolset.

I suspect you would lose this with an HDL front end, although they do seem possible in theory.

Frankly, the thought of designing a switchmode power supply using an HDL scares me. Designing a microstrip filter using an HDL seems nigh on impossible. (Hint: both these applications require careful layout, which is something that can be more easily expressed with a graphical entry tool.)

Regards, Allan.

Reply to
Allan Herriman

Hi Allan,

I tend to agree with your opinions. I just wanted to add that PCB layout tools that generate VHDL/Verilog netlists are very useful for system level simulation. Obviously this is not the information the original post was attempting to obtain but I wanted to throw it out there for others to contemplate.

Matt

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Reply to
Matt

I was always considering VHDL as behaviur/logic (netlist on functional gates) specification language. There are no means to add more detales required at PCB layout abstraction layer. VHDL has no means to describe placement, traces and device packages. I'm I missing missing something?

Reply to
Valentin Tihomirov

In principle, all this information could be stored in VHDL attributes. Attributes were designed for precisely this reason - attaching information to a VHDL object that makes no sense in VHDL, but must be passed to other tools. In practice, however, the result would be a disgusting mess.

Stick with a decent schematic package that can generate a VHDL netlist. Use that VHDL netlist for your pre-layout functional simulations, and use the conventional schematic-to-PCB tools for layout.

-- Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

Matt, it is true that they are useful for system level simulation. But the way of the development is IMO just the opposite: _first_ you do a simulation, also on system level, _after this_ you design your chips and board. For the system level simulation you need a HDL entity, like ¨Board¨ that connects the HDL Units representing the chips. You can do this by the Testbench unit, but IMO it is a better approach to separate the testbench and board functions. And you are there: you have a ¨Board¨ HDL that contains all inter-chip connections, it would be perfect to use this for PCB Netlist generation.

I made already a try with this, but did not succeed.

Janos Ero

Reply to
erojr

I think the part you are missing is that Symon wants to replace the schematic portion of the PCB layout software. I does not look to me like he was talking about replacing the layout portion. Maybe some people put layout info on the schematic, but I think most do not.

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Reply to
Duane Clark

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Hi Allen, Thanks for the reply! The tool I use at the moment, ORCAD, has separate layout and schematic entry bits. So, I agree that layout, i.e. drawing the traces, makes no sense in VHDL. However, the schematic entry is a pain in the @rse, after all it's just wiring up components to each other. You end up typing in lots of attributes anyway, part numbers, value, package size, pcb footprint. Seems to me that the physical wiring of the parts is perfectly feasible in HDL, and I can use Perl scripts to speed things along, like I do with VHDL for my FPGA innards designs. Maybe for some things like a SMPS, a diagram is very useful, perhaps necessary. However, for connecting a DRAM to a FPGA, the picture adds very little if anything. Some kind of hybrid is called for, like we already can do with logic inside FPGAs. Also, I would expect a HDL to be just as good at pin-swapping / gate swapping, but, once again, I agree that layout remains inherently graphical. As you point out the geometry of the traces is vital, and often forms part of the circuit.

Anyway, back to ORCAD! cheers, Syms.

Reply to
Symon

Thanks Duane, you've got it exactly! I re-read my OP and can see I wasn't too clear! (Ah, the perils of posting at the end of a busy and frustrating day!!) I've posted again to try to clarify what I'm banging on about. Cheers, Syms.

Reply to
Symon

I agree completely with you about the advantage of HDL for "schematic capture". Typically when you design a digital circuit you are making lists of bus names that connect to pin names or numbers... you just do this graphically rather than in an editor. This is actually more work of course, than just making the list as text. But most people are "comfortable" with schematics. The advantages of using schematic with layout really comes from the shared library rather than any inherent feature of schematic capture.

I remember a coworker who was telling me about a project from "hell" he had worked on at his last job. He inherited the work from a designer who had left and the docs were text lists of pins to nets, NO schematic! This guy could not work that way and ended up doing very poorly on that project.

Besides, isn't a schematic a nice thing to look at? Well, maybe not...

Would you be willing to write your design in a PCB program's netlist format? If you pick one that is popular (like PADS), it is portable in that most packages will import it.

--
Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

I agree completely. Keeping track of 300+ FPGA user I/O pins is hard enough in a spreadsheet or HDL. It's pretty much impossible on a schematic. Integrating the FPGA design and board design also has to be a Good Thing.

- Larry [who would s/VHDL/Verilog/g in the above]

Reply to
Larry Doolittle

I agree that the "netlist capture" portion of PCB schematic capture could be more easily done with vhdl or verilog. I like to look at a schematic too, but let's have the machine draw it!

Most large digital components have a free vendor-supplied BSDL file that could be converted to an entity with a script.

All of the architectures could be null for the purpose of netlist capture.

The top_pcb.vhd file would be formatted like a testbench with all of the signal (wire) declarations, entity instances, and port maps.

A simulation compile could find unintended shorts and opens, and a viewer could display a schematic for checking wires and entity instances.

A script could process top_pcb.vhd to create a netlist compatible with PADS, Allegro etc for layout.

The top_pcb.vhd file could be used again when the fpgas code is complete for a board level digital simulation.

-- Mike Treseler

Reply to
Mike Treseler

You are actually looking for a hybrid - as you say R's and C's do not HDL well.

The NETLIST formats of most PCB systems is quite simple, and some import many variants.

Better packages allow you to MERGE and CHECK netlists (ie split imports), so you could create a Analog Schematic + Block structure/IC number in Schematic (to keep BOM correct) and then move to HDL for digital interconnects.

If the device ( eg U1 TQFP100 ) is already imported via the SCH leg, all your HDL->NET has to do is handle the PinNumber -- NetName collections.

That should not be too hard for someone used to scripts.

You can also go backwards - eg after PINSWAP, a PCB script can create the PIN - Name list in the HDL format, for manual paste.

-jg

Reply to
Jim Granville

Janos -- agreed on the system simulation up front.

Agreement here as well. However I am not talking about Board = Testbench. Let me clarify. :-) "Board" is what I am talking about. Here testbench instantiates the "board" which instantiates "chips", resistors, capacitors, connectors etc. The tools generate "Board" from either a schematic capture tool or more importantly, the PCB tools. The reason I would prefer PCB tools is that if there are problems in the layout these could be detected in the simulation. All of this is automated to reduce human error. The things that you can catch are those things that DRC normally doesn't catch like incorrectly wired connectors and components.

I am talking about the opposite approach. PCB netlist is used to generate "Board".

-- Matt

Reply to
Matt

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