Hello everybody,

I need help in dealling with hard macros (in vhdl). I want to instantiate my macro in a vhdl design.

any one have an idea how to do it ? I tied to do as instantiating vhdl modules but the synthesizer does not recognize my macro.

Plz help.

thanks in advance.



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You likely haven't included the file that has the VHDL component definition for the hard macro. Read the instructions for the hard macro for how to go about including that in your project.


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Hi, what synthesizer? You missed to mention. There are many, and each dealing different with this. If you have a real hard macro, consisting of a pre syntesized netlist, the synthesis tool doesn't have to touch it at all. Your instantiation will be recognized as a black box (that's how Xilinx XST calls it, other tools may act differetn), and the Macro- netlist will be added to your design at a later stage of the implementation. Provided that you have set the Macro-Path information correctly in the tool properties.

Have a nice synthesis Eilert

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