Hi, I'm trying to design my system using partial reconfig and bus macro. Routing a module, I obtain this error for some signals:
ERROR:DesignRules:579 - Netcheck: The signal POS_I was found to be routed with nodes in two route area. This is not permitted for Modules in partial reconfiguration mode.
Now, I've imposed the area constraints, and all the signals are internal to the module. Analizing with FPGA_Editor, this signals correspond to LUT placed on the boundary of the module area. Can someone help me?
Another question. Somewhere I read I can't use LUT to pilot enable signal of bus macro three-state buffer. This means I have to pilot them with I/O pad? If I use a direct allocation LT