VHDL level simulation of JOP is now available ;-)
The actual version of JOP at the usual download page
formatting link
now contains (hopefully) all necessary file to run a simulation with ModelSim or a different VHDL simulator.In directory vhdl/simulation you will find:
- A test bench: tb_jop.vhd with a serial receiver to print out the messages from JOP during the simulation * Simulation versions of all memory components (vendor neutral) * Simulation of the main memory
In directory modelsim you will find a small batch file (sim.bat) that compiles JOP and the test bench in the correct order and starts ModelSim.
A (very) simple step-by-step introduction can be found at:
formatting link
It would be nice if somebody can try the simulation to check whether all scripts and directories are correctly set.
Cheers and thanks for checking it out ;-), Martin
---------------------------------------------- JOP - a Java Processor core for FPGAs:
formatting link