Low power SBC with large memory

I've got an application that needs an SBC (a redundant pair, actualy) which will survive 24 hours on battery power. I either spec a bank of big batteries, or find something less hungry than the 12-watt Ampro board I was originally looking at.

I need Ethernet, 4 RS232 ports, USB, and 512MB of DRAM.

I did some searching for Alchemy or XScale SBCs, but everything strikes out on the memory requirement.

What's the lowest-power big-memory SBC out there? Thanks.

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Getting much below those 12 Watts is going to be near enough to impossible to not be worth trying, I'm afraid. The problem is the 512 Megs of DRAM. I don't have hard numbers at hand, but from the technically oriented reports on laptop PCs I got an impression that

512 MB of DRAM may well eat a good fraction of those 12 Watts all by itself.

So prepare to bite the bullet and get a serious battery. 12 Watts for a full day ==> a full-size car battery. Per SBC. Or consider a UPS system with higher energy density than a lead-acid accumulator. Fuel cells look promising on that front.

You may already be looking at it.

Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.
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Hans-Bernhard Broeker

The geode sbc have ethernet, 1 RS232, 4 USB and 512MB/1G DDR2. It consumes about 5 watts. You can use additional USB to RS232 converters. We are planning to run it from a 12V solar panel ourself.

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Have a look at the VIA boards in mini-itx form factor. We had one of them running with 8W including hard disk with Linux. The same configuration with Win2k took 34W though. But with an XP embedded the consumption should come down.


Ing.Buero R.Tschaggelar - http://www.ibrtses.com
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Reply to
Rene Tschaggelar

Unless modern DRAMs are really different from old DRAMs, a single readout will always require writing the whole row back into memory cells. Thus, the larger number of memory accesses, the larger the power consumption.

If the processor sleeps most of the time, the DRAM power consumption should drop dramatically. Ultimately, the minimum power consumption depends of the refresh consumption. Thus, some assumptions about the processor duty cycle should be available, before determining the DRAM power consumption.

Various DRAM cycles with a single RAS but multiple CAS accesses, will consume less power, since the CAS only cycles would activate only the column output selectors after the full row has once been processed by the sense amplifiers during the RAS cycle.


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Paul Keinanen

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