keep_hierarchy in project manager

Hi,

I'm using ISE 5.2.03, using XST Verilog flow.

I can't turn keep_hierarchy on in the Project Manager.  There is no
field to do so in the Process - Properties - Synthesis Options dialog
(which is where the documentation says it should be).

My problem is that my RLOCs don't work because XST flattens the
hierarchy and puts all my macros into the one HSET!  I would like to try
with keep_hierarchy on, but the *&(#$% GUI won't let me.

Help!
Allan.