Hello The question is in the subject: is there such a thing? How to make an Altera post-p&r simulation work when a setup violation occurs on an input register?
-- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/
-- Mike Treseler
How about synching the testbench data output to the chip input clock? I don't think there is any value to allowing the setup time to be violated in a simulation since there is no simulation equivalent to metastability.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.