ISE5.2 to ISE6.1

|> Anybody having similar problems?

Me too. A design for a 2S200 which needs to run at 130MHz (5.1 achieved ~133MHz without floorplaning) is slowed down with 6.1 to about 110MHz. "High effort" etc. does not help at all. Looking at the timinganalyzer output, it seems that MAP ignores the first carry chain block and uses regular logic and routing instead, thus stealing about 2ns :-(

I've had similar problems. A few here have mentioned the problem you have. I have a problem with timing not being met (was met on 5.2i) even though I have several timing constraints and placement constraints that should help.

I'd agree with your final statement, but it really isn't a 'nice GUI'. It's more like a slopped-together GUI to get the task done, but pays little attention to the technical details that FPGA engineers desire or the good GUI design that can provide such nice results. As GUIs go, it's most comparable to the crap that Matlab added to their 6.0 stuff.

And don't even get me started on ECS. I've seen schematic capture programs done as an assembly-language programming course final project that are better than that.

Jake

I agree. 4.2 had bugs, but it was possible to work around them. Trying to compile the same project under 5.x and 6.x is a disaster. The bugs are so bad that it won't even synthesize.

: |> Anybody having similar problems?

: Me too. A design for a 2S200 which needs to run at 130MHz (5.1 achieved ~133MHz : without floorplaning) is slowed down with 6.1 to about 110MHz. "High effort" etc. : does not help at all. Looking at the timinganalyzer output, it seems that MAP : ignores the first carry chain block and uses regular logic and routing instead, : thus stealing about 2ns :-(

Perhaps send your code to Xilinx for inclusion in their regression test suite. However after the VLGINCDIR happening ( it was broken until 5.2 and is broken again in 6.1) I wonder if there is any...

Bye

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Been there - done that, PAR just crashes now! "Will be fixed in next service pack" is as far as I can get with 6.1, so its back to 5.2 for me!

Cheers, Martin

Hi, I am facing the same problem. I have a design in XC2S400E which is working well in ISE 5.1 sp3 and met all timing requirements. When I moved to 5.2 it failed to give required timing. I did not worry b'coz I knew that they are coming up with 6.1. Now when I synthesized/implemented my design in 6.1 (latest sp), it is giving the same result as in 5.2 (i.e. it is unable to meet the performance of

Regards, Nagaraj CS

I see a new post started about this elsewhere in this group. My one comment is that the FAEs who post here recommend that you call the hotline and open a case on this. The sooner they learn of your problem the sooner they can address it and keep it from being *my* problem...

Nagaraj wrote:

Tom Seim

Did you also install the service pack?

I have had problems with 5.1,5.2 and 6.1 on XC2V4000 and XC2V6000 designs. My original designs were done on 4.x. I believe that the problem is in migrating the 4.2 designs to 6.1. I use 4.2 to synthesize and route, and Impact 5.2 to program the FPGAs. I have reported every problem to Xilinx. New designs that are originated using 6.1 work OK.

Bill Hanna