Hi all,
I have updated my Xilinx software to 6.1 a few days ago and it looks like I am in for a ride; the design that worked well under the previous version (5.2 with all service packs) wouldn't even go through PAR anymore!! I managed to work around this by setting thr effort level to maximum for the place&route but when I program the FPGA (XC2V4000-5) with this new bitstream my board doesn't work anymore!!? Anybody having similar problems? I guess I shoild have known better: the service pack for this latest software creation arrived before the CD with the software did! In my humble oppinion the best software from Xilinx was 4.2, it's all downhill from there; it seems that a nice GUI is valued more than a decent and consistent PAR algorithm these days.