I still don't know what you mean by "the design fails". Do you get a netlist or bit file for the FPGA? Does the simulation not run as you expected? Does the FPGA not run as expected?
I went back and looked at your original post. There may be other problems (sensitivity list, clock clause, etc.) can you post the entire process for us?
Andy
Ok, I would try to explain as better as I can.
This is my block design:
Input Block ====> FIFO input ==> Any Algorithm => FIFO output => Output Block
As you could see, the FPGA (a Virtex IIPro) has two inputs/outputs ports. I use one of the for the input, and another one for the output. The ports intarfaces are implemented as Input Block and Output block, and this works fine. Each of them is conected with a FIFO.
So the system receives a certain number of packets, then it process them and finally it retransmits them. That is:
Receive 1 2 3 4 5 6 7 8 9 from a DSP connected by a 32 bit bus. Process (for example *2): 2 4 6 8 10 12 14 16 18 Returns 2 4 6 8 10 12 14 16 18 to the DSP.
Every block works fine with the exception of the FIFO output block.
I have tried the next designs for this block: - First of all I probed with the same design as Input FIFO, but the DSP didn't receive back any packet. I suppose I was not able to resolve delay problems in clock synchronization (this is what I call "design fails", that is, DSP didn't receive back any processed packet). - For this reason I decide to probe a LIFO design in which I use the complete size of the LIFO (64 positions of 32 bits). Then I only have to read from position 0 (that is the reason why I need to use Mod operator).
This is the code for this block.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
------------------------------------------------------------------------------- entity simpleFIFO is generic ( bits : integer := 32; -- # of bits per word words : integer := 64); -- # words in memory port ( reset : in std_logic; clk : in std_logic; wr_en : in std_logic; rd_en : in std_logic; data_in : in std_logic_vector(bits-1 downto 0); data_out : out std_logic_vector(bits-1 downto 0); fifo_full: out std_logic; fifo_empty: out std_logic; debug : out integer range 0 to words-1); end simpleFIFO;
architecture a of simpleFIFO is type vector_array is array (0 to words-1) of std_logic_vector(bits-1 downto 0); signal memory : vector_array;
begin process(clk, reset, wr_en, rd_en) variable addr : integer range 0 to words-1:=0; variable fifo_empty_v : std_logic; variable fifo_full_v : std_logic; begin if reset = '1' then fifo_empty_v := '0'; fifo_full_v := '0'; addr := 0; else if(clk'event and clk = '1') then
if addr = words+1 then fifo_full_v := '1'; else fifo_full_v := '0'; end if;
if(wr_en = '1' and fifo_full_v = '0') then memory(addr)
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