CALL FOR PARTICIPATION _____________________________________________________________________ International Workshop on Applied Reconfigurable Computing (ARC 2005)
URL:
To register, please fill in the form in
PROGRAM:
------------------------------- Tuesday 22 February 2005
-------------------------------
9:30 Registration
10:00 Opening Session
10:15 Invited Speaker: Pedro Diniz University of Southern California / Information Sciences Institute, CA, USA "Exploiting Data Reuse in Modern FPGAs: Opportunities and Challenges for Compilers"
11:00 COFFE BREAK
11:15 SESSION A: (3 distinguished papers) APPLICATIONS I
11:15 "Optimized FPGA Implementation of a Multi Program PCR Measurement System in DVB-T" Authors: C. Mannino, H. Rabah, C. Tanougast, Y. Berviller, M. Janiaut and S. Weber Affiliation: Laboratoire d'Instrumentation Electronique de Nancy (L.I.E.N.), U.H.P., Faculte des Sciences, France
11:40 "An FPGA Implementation of a Flexible Secure Elliptic Curve Cryptography Processor" Authors: T. Kerins, W. P. Marnane, E. M. Popovici Affiliation: University College Cork, Ireland
12:05 "Network Intrusion Detection Systems on FPGAS with On-Chip Network Interfaces" Authors: Chris Clark, Craig Ulmer Affiliation: Georgia Tech, Sandia National Labs, USA
12:30 LUNCH
14:00 SESSION B: (5 regular papers) DYNAMIC RECONFIGURATION AND ARCHITECTURES
14:00 "Function Replacement of Hard Real-Time Systems using Partial Reconfiguration" Authors: Thomas Reinemann, Roland Kasper Affiliation: IMAT, Otto-von-Guericke-University Magdeburg, Germany
14:20 "A Methodology for Hardware Tasks Scheduling Optimized in Time for Partial and Dynamic Reconfiguration of FPGAS" Authors: Remy Eskinazi, Paulo Maciel, Manoel Eusebio de Lima, Paulo Sergio Nascimento, Abel Guilhermino, Carlos Valderrama Affiliation: Federal University of Pernambuco, Brasil
14:40 "Towards a Runtime Reconfigurable Network-on-chip-based Network Processor" Authors: Jürgen Foag, Roman Koch Affiliation: University of Luebeck, Germany
15:00 "Adopting the Small-World Network in Routing Structure of FPGA" Authors: Masahiro IIDA, Shinya ABE, Hisashi TSUKIASHI, Ryoji OGATA, and Toshinori SUEYOSHI Affiliation: Kumamoto University, Japan
15:20 "Novel Switch-Block Architecture Using Reconfigurable Context Memory for Multi-Context FPGAs" Authors: Wei Sheng CHONG, Masanori HARIYAMA, and Michitaka KAMEYAMA Affiliation: Tohoku University, Japan
15:40 COFFE BREAK
16:10 SESSION C: (5 regular papers) APPLICATIONS II
16:10 "Realisation of Real-Time Control Flow Oriented Automotive Applications on a Soft-core Multiprocessor System based on Xilinx Virtex II FPGAs" Authors: Katarina Paulsson, Michael Hübner, Hong Zou, and Jürgen Becker Affiliation: Universitaet Karlsruhe (TH), Germany
16:30 "Optimise FPGA Implementation of an AES Algorithm for Embedded Application" Authors: T. Liu, C. Tanougast, P. Brunet, Y. Berviller, H. Rabah, and S. Weber Affiliation: Université Henri Poincaré Nancy I, France
16:50 "Efficient Decoding of Variable-Length Encoded Image Data on the Nios II Soft-Core Processor" Authors: Peter Mårtensson, Jans Persson, Shang Xue, and Bengt Oelmann Affiliation: Mid Sweden University, Sweden
17:10 "An Efficient, Low Resource, Architecture for Backpropagation Neural Networks" Authors: Pedro O. Domingos, and Horácio C. Neto Affiliation: INESC-ID, IST, Portugal
17:30 "FPGA Based Architecture for the Data Acquisition Electronics of the Clear-PEM System" Authors: J. Varela, P. Bento, C. Leong, I. C. Teixeira, J. P. Teixeira, J. Nobre, J. Rego, P.Lousã, P. Relvas, P. Rodrigues, and A. Trindade Affiliation: LIP-Lisboa, Lisbon, Portugal; Universidade Técnica de Lisboa, Instituto Superior Técnico, Lisbon, Portugal; INESC-ID, Lisbon, Portugal; INOV, Lisbon, Portugal
------------------------------- Wednesday 23 February 2005
-------------------------------
8:45 SESSION D: (3 distinguished papers) ARCHITECTURES AND APPLICATIONS
8:45 "A RISC Architecture Extended by an Efficient Tightly Coupled Reconfigurable Unit" Authors: N. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis Affiliation: Section of Electronics and Computers, Department of Physics, Aristotle University of Thessaloniki,54124 Thessaloniki, Greece
9:10 "A Dynamic Optically Reconfigurable Gate Array using Dynamic Method" Authors: Minoru Watanabe, and Fuminori Kobayashi Affiliation: Kyushu Institute of Technology in Japan, Japan
9:35 "A Fault Tolerant Gesture Recognition System for Mobile Robot" Authors: Vanderlei Bonato, Márcio M. Fernandes, and Eduardo Marques Affiliation: Institute of Mathematics and Computing Sciences, University of São Paulo, Brasil
10:05 COFFE BREAK
10:35 SESSION E: (5 regular papers) TOOLS,TECHNIQUES, AND METHODOLOGIES
10:35 "A Methodology for Parameterized Algorithm Design to Support Flexible FPGA Based System Design" Authors: Aparna Nagargadde, Sridhar Gangadharpalli, and Sridhar V. Affiliation: Applied Research Group, Satyam Computer Services Limited; Entrepreneurship Centre, Indian Institute of Science Campus, Bangalore
10:55 "Pipelining Sequences of Loops: A First Example" Authors: Rui Rodrigues, and João M. P. Cardoso Affiliation: University of Algarve, Portugal
11:15 "Open Architecture Hierarchical Placement for FPGA Datapath Designs" Authors: Dong Kwan Kim, Cameron Patterson, and Peter Athanas Affiliation: Virginia Polytechnic Institute and State University, USA
11:35 "Optimizing Area on the Generation of Specific Circuits in FPGAs for SIMD Applications" Authors: Germán León, José M. Claver, and Germán Fabregat Affiliation: University Jaume I, Spain
11:55 "A Test Infrastructure for Compilers Targeting FPGAS" Authors: Rui Rodrigues, and João M. P. Cardoso Affiliation: University of Algarve, Portugal
12:10 Closing Session