Hi,
I'm working on a University project that requires ddr-ram interfaced to a Vertex-EM device. I am basing my design off xapp200 from xilinx. The design uses DLLs to deskew the system clock and ddr-ram clock. The signal fed back to the DLLs (sys_clk_fb) is apparently the ddr clk. What I don't understand is where I take this signal from. Should I have tracks on my PCB comming back from the ddr-ram chips to inputs on the fpga? Or can the feedback signal come from inside the fpga?
I am a little lost as to how the DLLs manage to sychronise the two clocks. Any help would be appreciated.
Thanks.
Michael.