PIC and 10-Bit ADC

Please tell me what document told you this. A PIC model number would also be helpful to us. Since you didn't specify one, I will pick the

16F88.

Hardly. ADRESH and ADRESL are only 8 bits each in size. The 10 bit result can be left justified or right justified depending upon another SFR bit setting. The ADFM bit in the ADCON1 register determines whether the result will be left or right justified accross the two ADRESx registers.

We would need to know what you are using for Vref to tell you that. Assuming that you are using a 5V Vcc as your Vref then each increment would correspond to (5/1024) or about 4.88mV.

these

10-bits?

Again, the registers are only 8 bits in size. That's why there are two of them. To achieve 10 bit precision you will need the data from each register. If you only want an 8 bit result (giving 4.88mV * 4 or about

19.53mV per increment) then specify left justification by clearing the ADFM bit in ADCON1, take the value of ADRESH and ignore what's in ADRESL.

Actually, I think you can choose left justified (upper 8 bits in ADRESH, lower 2 bits in high end of ADRESL, others zeroed) or right justified (high two bits in low end of ADRESH, others zeroed, lower 8 bits in ADRESL)

2.564 out of 5 with a 10 bit resolution is (2.564/5)*1023 = 525 (rounded to the nearest integer) decimal or 1000001101 binary.

If set up for left justified, ADRESH would hold the left 8 bits of that, or 10000011 and ADRESL would hold the right two bits in its left end with the rest filled with zeros, or 01000000.

If set up for right justified, ADRESH would hold the left 2 bits of that value in its right end, with the left bits filled with zeros, or

00000010 and ADRESL would hold the right 10 bits or 00001101.

If you just want the voltage measured using the most significant 8 bits and intend to waste the lower two bits, use left justification and take ADRESH as the result. If you intend to do treat the result as a 10 bit binary value that fits in a 16 bit space, (for instance, if you intend to do some 16 bit math on it to perform digital filtering) you use right justification and both registers.

If you use left justification and the ADRESH value as an 8 bit conversion (0 to 255 range), each count in ADRESH represents 5 volts divided by 255 or .01961 volts. If you use right justification and use both resistors to measure the voltage as a 16 bit number (with only 10 of those bits ever used, each count represents a voltage of

5/1023 or .00489 volts. But your program will have to make magnitude decisions based on two byte programming, so each value comparison will be a little more complicated.

AIUI the divisor to use is 256.

1024 :-)

There are 256 possible voltages to be measured, but one of them is zero, so the range is divided by 2^8-1.

One less, for the same reason. 1024 end points, but only 1023 spaces between them.

magnitude

Assuming a Vref of 4.096V and an "ideal" 10 bit ADC to make things simple, a conversion result of 0 would actually encompass the range of

0V-.00399R Volts; the second range for a reading of 1 is .004V to .00799R Volts. Consequently the final range would be for (1023*.004) 4.092V thru 4.096V. Is that not correct?

The way I see it, each level is ideally converted with an accuracy of

+,- 1/2 LSB, except for the first and last level. 0 is converted to an accuracy of -0, +1/2 LSB and the highest level is converted to an accuracy of -1/2LSB to +0.

of

(1023*.004)

I can't find any mention of excepting the first and last levels in the datasheet nor in the mid-range reference manual. I can't help but wonder why precision voltage references obviously assume 2(n) steps and not 2(n)-1. FWIW, my John Peatman book seems to agree with me. Perhaps an ADC expert could shed some light on this?

Why is the last level (255) only representing a range up to Vref - 1/2 LSB? Given your analysis, it only gets within 1/2 LSB of Vref. To me, that means you have an extra 1/2 LSB left over to explain... ;)

However, if you assume that the output is based on the floor of the range (which I believe is the case) then everything works out properly:

0*Vref/256 to 1*Vref/256 -> 0, 1*Vref/256 to 2*Vref/256 -> 1, 2*Vref/256 to 3*Vref/256 -> 2, ... , 255*Vref/256 to 256*Vref/256 -> 255.

Unless I'm miscounting, that means you have 256 voltage ranges, which map neatly to the 256 values that your 8 bit ADC output can take on.

OTOH, the difference between 1/255 and 1/256 is so small that this will make absolutely no difference for most situations, except that you won't be able to use shifts to do the math.

--
Regards,
  Bob Monsen

We should take care not to make the intellect our god; it has, of
 course, powerful muscles, but no personality.
    Albert Einstein

I think I have made a mistake about the voltage per step being 1/2^n-1 times the full scale voltage, because that conflicts with the first and last levels being at 1/2 LSB value. But I think it is true that the first and last step are 1/2 LSB, while all the others are 1 LSB wide. Here is an excerpt from a National data sheet for an 8 bit successive approximation A/D converter:

(begin excerpt) Code transitions occur midway between successive integer LSB values. The LSB width for the ADC081S101 is VA/256. The ideal transfer characteristic is shown in Figure 5. The transition from an output code of 0000 0000 to a code of

0000 0001 is at 1/2 LSB, or a voltage of VA/512. Other code transitions occur at steps of one LSB. (end excerpt)

Unfortunately, the voltage versus count diagram immediately following does not reflect this paragraph.

However, I have seen others that do. For instance, all the voltage versus count graphs in this Maxim application note show the first step as 1/2 LSB and all the rest as 1 LSB.

s

Here is another reference that mentions both the first and last step=20 being only 1/2 LSB and the voltage per step (1 LSB) being (1/2^n -1)*Vref= :

(begin excerpt) The width of one step is defined as 1 LSB (one least significant bit)=20 and this is often used as the reference unit for other quantities in the specification. It is also a measure of the=20 resolution of the converter since it defines the number of divisions or units of the full analog range. Hence, 1/2 LSB represents=20 an analog quantity equal to one half of the analog resolution.

The resolution of an ADC is usually expressed as the number of bits in=20 its digital output code. For example, an ADC with an n-bit resolution has 2n possible digital codes which define 2n=20 step levels. However, since the first (zero) step and the last step are only one half of a full width, the full-scale=20 range (FSR) is divided into 2n =96 1 step widths. Hence 1 LSB =3D FSR/(2^n - 1) for an n bit converter. (end excerpt)

You appear to be right about the first transition starting at 1/2 LSB after 0. This makes the jagged line on the graph of voltage vs values have a smaller difference between the 'theoretical' line, thus making the digitization error smaller.

However, they are wrong about that divisor, at least for some ADC chips. It is pretty confusing, I'll agree, but if you just make yourself a graph of input voltage vs output codes, you see that the last value represents

3/2 LSB. (This is also pointed out in an Analog Devices datasheet for the AD9226, page 7 and 19.)

The voltage is exactly represented at the midpoint of each step, so there is a possible error for each bit of up to +- 1/2 LSB. Now, imagine a 2 bit converter (so to speak...) that uses a FS Vref of 1V. It'll have output transitions at 1/8, 3/8, and 5/8V. That means that for an output value of 1, the input voltage was 1/4 +- 1/8. For an output value of 0, the input voltage was 0 +- 1/8. etc. So, the input voltage is within 1/2 LSB (1/8V) of output/4.

The AD9226 actually considers input voltages that are greater than -1/2LSB to be valid inputs, and considers input voltages above FS - 1/2LSB to be

*invalid*. The out of range output pins are defined this way.

However, it is possible that the scale is stretched on other converters. If the scale is stretched, then for those converters, the LSB may actually be as you say. For our 2-bit converter, that would make transitions at

1/6, 3/6, and 5/6. This would result in a maximum error of 166mV as opposed to 125mV with the other encoding scheme, and thus a bigger encoding error.

--
Regards,
  Bob Monsen

We should take care not to make the intellect our god; it has, of
 course, powerful muscles, but no personality.
    Albert Einstein

of

(1023*.004)

of

that

properly:

map

That's roughtly the way I see it. The only thing I would change is that your numbers are a little bit ambiguous in that you allow one voltage to return two different values. That's why I went with the 999R thingy. It seems to me that precision (.1%) voltage references indicate that

2(n) is the appropriate divisor.

you

True, but we're being pedantic here. ;-) Besides, I really want to know which is correct. With Google it's a split decision. Microchip documentation seems to agree with 2(n), but others agree with John.

Now there's somebody worth quoting. (;-)

the

and

Perhaps

(1/2^n -1)*Vref:

This all sounds simple/reasonable enough.

I'm with you so far. ;-)

Hmm.

I'm kinda dumb, so I don't really get how they arrive at that completely. :-? I can see that it might be hard to acheive + or - resolution at the extreme ends of the scale since you can't really be less than 0 or greater than Vref so that would seem to remove half of its range, making the first and last steps half-width.

The Peatman books show a stair-case with input voltage on the horizontal scale and the ADRES value vertically. The first step is flat (ADRES =

0) for a full step width. The last step peaks early in the way that I described (returning 0x3FF for a voltage less than Vref. Next time I'm tinkering with the PIC ADC, I'll do some measurements to see where the first (0x00 -> 0x01) and last (0x3FE -> 0x3FF) transitions occur. It should prove kinda interesting to see if the first transition occurs at 2mV (4.096 reference).

I think it depends on the converter. I bet some do it one way, and others do it the other way. It is an arbitrary choice. One way gives you more steps, and thus less quantization error, while the other way gives you a larger usable range.

--
Regards,
  Bob Monsen

Imagination is more important than knowledge...
    Albert Einstein

Yes, we should pick a particular A/D and nail that one down, first. Then we will be in a position to look for exceptions.

Look at figure 14, page 19 of this one:

--
Regards,
  Bob Monsen

You cannot simultaneously prevent and prepare for war.
    Albert Einstein, (attributed)

I looked, but it doesn't make sense to me. The -FS and +FS ends of the scale are not symmetrical, with the lowest output transition taking place at (-FS) +1/2LSB, but the highest transition taking place at (+FS) -1 1/2 LSB, which can't be correct. Can it? Is there any A/D data sheet that gets everything correct? No wonder there is disagreement on how these things work.

It's been jolly interesting following you guys discussing this.

I rather think you left the OP at the starting line though ! ;-)

Graham

You'll have that, sometimes. I'm here on a generous impulse, but when something comes along that serves my education, I have no problem taking a detour. We spent quite a bit of effort explaining the left and right justification modes and ranges of the O.P.'s A/D, before we left him to explore this detail. And just because we are doing this, you are certainly free to continue with the hand holding.