Hi I want to make a project that uses an image sensor (any perhaps a low power cmos from Micron or Kodak) connected to a FPGA (or CPLD). with the apropriate VHDL or Veralog code.
Has anyone done this who would be willing to share there hardware and/or software designs to get me started? Or is there any examples on the web that I can explore?
Martin mart NO inb SPAM AT magma DOT ca
Remove the NO SPAM and put no spaces. Also replace the AT for @ and the DOT for .
On a sunny day (Tue, 27 Jan 2004 11:18:07 -0500) it happened bob wrote in :
Somebody in Spain did a VHDL version of my mcam soft, uses the Creative webcam II look for document: Sistemacapturaimagenfin.pdf This webcam uses a 8052 processor to talk to the sensor itself. So the fpga talks to the 8052. The sensor is 4 bits bus with serial control, but I no longer have the datasheet. It is in Spanish. This sensor is likely superceded by better ones.
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for my C version. The VHDL version will learn you how to emulate a PC parport.... I think, given the datasheet of the sensor, it is pretty straight forward. Talking directly to the sensor eliminates such protocols as par port / usb, whatever. But you may still need that to send the data anywhere else... JP
I think this directly connects with a CMOS sensor (figure 3)
Article (from Xcell Journal)
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(get the pdf with pictures at page bottom)
Alternative location:
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"FPGA Code
Most of the system functionality is implemented in the Xilinx Spartan-IIE FPGA. The code is written in Verilog HDL and is available for download at my Elphel website under the GNU/GPL (general public license) license. It is designed around a four-channel SDRAM controller that uses embedded block RAM modules as "ping-pong" buffers to provide quasi-simultaneous block access for the following data sources and receivers:
Image data from the sensor, either processed or raw, one- or two-bytes per pixel, arranged as 256 (128) pixel lines Calibration data to the FPN elimination module prepared by software in advance, 128x16-bit blocks Data to the JPEG compressor, arranged as square blocks of 16x16 bytes CPU access to the SDRAM (normally used to read raw sensor data and write back the calibration data for the FPN elimination). The JPEG encoder uses two-thirds of the FPGA resources, as shown in Figure 3. The encoder consists of the chain of the processing modules, some of which use block RAM for data buffering and table storage: - Bayer-to-YCbCr converter - 8x8 DCT based on the Xilinx XAP610, modified to provide block-asynchronous operation and to increase dynamic range - Quantizator and zigzag encoder - RLL encoder - Huffman encoder - Bit stuffer."
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