Hi all,
Is that possible to put the busy signal (when the FPGA is configuring) in a float state.
I coupled an ARM7 and a SPARTAN-II, and busy signal of the FPGA is directly connected to a data_line of the ARM. As we are doing FPGA configuration over ethernet, busy line corrupt the ARM when it try to configure the FPGA.
There are two solutions:
-- change the schemetic
-- to be able to put busy line in a float state as an other IO line when FPGA is programming :
Are there any option in ISE to do that?
Laurent
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