I would like to implement a fast 16-bit parallel port on an x86 system for interface to an analog-to-digital converter. From a software standpoint I am wondering about the feasibility. The ADC provides TTL signals that are compatible with the IDE electrical specs (16 data and one data-valid clock). I can set the clock to meet any of the IDE PIO mode specs (modes 0-4). So it appears the the electrical interface is easy. How difficult would it be to read the 16-bit data directly from the IDE controller. Assume we are dedicating the secondary IDE bus to this task. I'm thinking along the lines of a simple "PIO like" implementation. The system would be dedicated to the data acquisition so inefficient use of the CPU such as polling is acceptable.
Thanks, Jim