I/O state of max7000s during power-up?

Sep 15, 2004 3 Replies
U

I'm using EPM7128S now.Some of the outputs connect to a Darlington array which controls some relays. So I want to know the exact state of these outputs during the Power-up.But the datasheet of max7000s doesnt mention it. Somebody tell me the voltage of I/Os is uncertain before the POR completed.Then how can I control them before the device running properly?


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R

By having external pull-ups or pull-downs.

Rene

Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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J

PLDs have internal Power On resets, IIRC Atmel specify ~3.8V POR release on 5V parts. (Altera should will be similar).

If your supply takes a really long time to climb to

3.8V, then you could have problems, but normally by the time there is enough system voltage to work the relays, you have correctly powered up the CPLD.

If it is vital the relays are never invalid, you could look to use Reset/Watchdog/hardwired logic to force a known, safe state.

-jg

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R

IMO, before the initialization, the pins are inputs in high impedance state. This is especially important because there is a time before the chip is programmed.

And it can also be that it takes a few development cycles until the prototype is programmed correctly. Make sure the external hardware is not fried before that.

As Jim said, an EEPROM based CPLD such as the EPM7128S is rather quick in booting, once it is programmed.

Rene

Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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