Hi,
I have a design which has Virtex5 LX30T.
On a particular IO, I have a external pull up of 4.7K, which connects to another device. I notice that at powerup that IO is driven down for
30msec before it gets tristated (and hence assumes state of logic high because of external pull up)I have filed the webcase for the same and awaiting the response.
Does anyone has encountered any such problem.
This behavior makes the board design little tricky, because unintentional toggling on the IOs may cause some devices on board to behave abnormally during powerup and may lead to potential problems.
I have a particular SFP device, whose SCK signal (I2C clock) is connected in this fashion. And this is causing the I2C state machine inside the SFP device to go in freeze state. I can only get around this problem by jack out jack in of SFP.
-- Goli
PS: I am not following any voltage sequencing, my VCCAux and VCCint is derived from LDO using VCCIO (which is 3.3 Volts)