Hello
I have implemented an multiplier in the following way: I always take 4 bits of my first operand and multiply it with the second operand. So in every step I generate 4 partial products which have to be added. This sum is stored in the accumulator. In the next clock cycle I take the next 4 bits, multiply it with the second operand, sum up the partial products and add this to my accumulator. This is performed a few times until I have processed all the bits of operand one. Then my result is stored in the accu. My implementation works fine but when I synthesize it I get a lot of "warnings", can somebody tell me what went wrong here?
Mapping all equations... Building and optimizing final netlist ... Register outp_0 equivalent to accu1_8 has been removed Register outp_1 equivalent to accu1_9 has been removed Register outp_2 equivalent to accu1_10 has been removed Register outp_3 equivalent to accu1_11 has been removed Register outp_4 equivalent to accu1_12 has been removed Register outp_5 equivalent to accu1_13 has been removed Register outp_6 equivalent to accu1_14 has been removed Register outp_7 equivalent to accu1_15 has been removed Register outp_8 equivalent to accu1_16 has been removed Register outp_9 equivalent to accu1_17 has been removed and so on...
The code for accu1 and outp looks the following:
if rst = '1' then op1 '0'); op2 '0'); outp '0'); accu1 '0');
elsif clk'event and clk = '1' then if load = '1' then op1