Rewrite the whole libraries, which model Xilinx primitives for all Xilinx FPGA/CPLD families and all speed grades? :-S
Mike Treseler wrote:
How to get lowest price for a ModelSim license?
Jun 12, 2006
25 Replies
No. Leave the primitives to synthesis. Leave the timing to STA.
-- Mike Treseler
STA?
Static Timing Analysis.
It's nearly impossible to prove that a design will work with simulation. Static Timing Analysis is a simulation-less proof mechanism. The tool uses clock periods and setup and hold times and propagation delays of the hardware to prove it a design will meet a specified timing.
A digital design flow should go basically like this:
1=2E Specify and make list of features. 2=2E Implement RTL. 3=2E Write functional simulations to test features exhaustively. 4=2E Test features. 5=2E Write design constraints. 6=2E Synthesize. 7=2E Run Static Timing. 8=2E Do timing fixes if necessary, go back to step 4. 9=2E Tape out or do whatever you need to do with your complete design.The point is you should never need to run timing sims. That said, I've never worked on a chip that didn't need them. All I can say is that you almost can't guarantee a circuit to be working through timing gate sims.
-Arlen GaLaKtIkUs=99 wrote:
Ugh! There is no need for that. As I said already on this thread, Icarus Verilog will (should) parse and ignore specify blocks and the end result is a perfectly good simulation. All you miss in this context is back-annotation support.
Any other problems simulating with Xilinx models should be posted in the bug tracking database. I *will* fix such bugs, because I do Xilinx work with Icarus Verilog regularly.
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
Why not just rewrite the ones you need, instead of ALL of them?
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