How to Find false path in a design

Question

Hi GuysWe have been knowing the false path and its nature but i am confusedas to how to identify a false path in a design having say 100 modules.We know that false path as defination that it is the path that isnever executed or sanitisized henceforth it is not included in theSTA . But the million dollar question is if the design is really bigthe how can one it so as to name it in the synthesis. I want to knowthe steps followed in the industry. I will value your comments and plsdo upload some relevant material or any case studyThanks in advanceVips

Jonathan Bromley · Accepted Answer

[...]Google for "false path" is a good start.  Here's a coupleof places you might look:PrimeTime, probably the best-known of the many statictiming analysis tools....FishTail, an interesting new tool that uses formal techniquesto identify false and multi-cycle paths....Note, these are not recommendations in any way - just twoproducts that I happen to be aware of.  I'm sure there are many more.  It's not really my field.-- Jonathan Bromley, ConsultantDOULOS - Developing Design Know-howVHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project ServicesDoulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UKThe contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

hans64 · Answer

Hi Vips,If you are not meeting timing and you have lots and lots of pathfailing then save yourself some major pain and get a copy of fishtail.I played with this software some time ago and I can tell you it isvery powerful. You just feed it your rtl and some constraints and outcome a set of SDC files for false and multi-cycle path. On top of thatif can also generate a set of assertions for you to verify thegenerated constraints.Hans

Mike Treseler · Answer

I use separate modules for each clock domainand run STA on those. I use "known good"synchronization techniques between the modules.   -- Mike Treseler

Jonathan Bromley · Answer

I should also have mentioned Blue Pearl's products... talked with some of the Blue Pearl guys at DAC today and they assured me their tools can find false paths thatcross design hierarchy boundaries in designs up to at least a million gates.  I haven't yet had a chance to try out for myself this interesting application of formal technology.-- Jonathan Bromley, ConsultantDOULOS - Developing Design Know-howVHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project ServicesDoulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UKThe contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

How to Find false path in a design

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