I have spent three-four days on several XPLA3 CPLD boards that I've designed (same boards) to determine why the JTAG is not working properly. I cannot initialize the chain to "read" what devices are on the boundary scan chain, nor will TDO change states. I can set "levels" on TDI, TMS, and TCK using the "Start Debug Chain" portion of the Xilinx IMPACT software.
I am using the Parallel IV cable and have read a few places it could be cable length issues? Does ANYONE have any type of experience with this? I've been wracking my brains out trying to figure out what's wrong.
I am using a "home-made" cable because my PCB is used in embedded application with limited space.
Even went to a BLANK PCB and stuffed only CPLD, linear regulator, and caps.
Any help is MUCH MUCH appreciated...
Thanks!