HDL simple survey - what do you actually use

I'm not good at writing reviews, but I'm very happy with MyHDL. It removes the pain that I mostly feel when writing VHDL. And using MyHDL is the first time that I write real testbenches and simulate.

Something that I can recommend to read about MyHDL are articles by Jan Decaluwe, the main author, at

. Especially this one: . Then Christopher Felton also has a couple of nice articles at fpgarelated:

Thomas

I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around.

For a reference I recommend: RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland.

Seems to be a $120 book. That's a bit steep even for HDL books.

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998

Bluespec SystemVerilog (BSV), which is actually nothing to do with SystemVerilog but is a high-level HDL derived from Haskell (including types, polymorphism, functional language features).

Since BSV is a bit niche, I teach SystemVerilog to undergrads and will use it for glue when necessary.

Talking to major IP vendors who provide both Verilog and VHDL versions of IP, the Verilog versions are a lot more popular.

Theo

I do.

It is true SystemC is more for the C/C++ aficionados. However SystemC has a lot going for it, here are some quick points:

1) You get a simulator and all the support libraries in source for free. 2) If you know VHDL then you can easily program in SystemC (same model of signals, processes, variables, delta cycles etc). No horrible blocking/non-blocking, wire/reg, race spaghetti. 3) It is easy to learn and you don't have to dive to deep into C++. 4) It is great for behavioural modelling. 5) You can choose from many free and commercial IDE's. 6) There is a free UVM library. 7) It runs on many platforms (you just need a C++ compiler) 8) There is a synthesisable standard (albeit somewhat outdated) 9) There are a number of SystemC translators/synthesis tools available. 10) You can "embed" the OSCI engine into your product (bar the usual license agreement) 11) It is relative easy to bolt on any library you like Qt/SDL2. 12) It has the best TLM capabilities (SV uses the same models) 13) It has transaction recordings capabilities (SCV) 14) It has some assertion capabilities (PSL support would be great!) 15) It supports randomisation (like rand in SV) and contains a constraint solver.

The free nature of it is both a blessing and a curse. Because it is free commercial support is somewhat sluggish (Cadence being the exception). There are (AFAIK) no free RTL style IDE's which works as easily as VHDL/Verilog on Modelsim/VCS/NCSim/Riviera/etc. Using sc_trace and GTKWave is just too painful. There are products like Vista that come close but still not as slick as Modelsim. I tried to write something but underestimated the amount of free time it takes to create something barely usable.

So for pure RTL designs I agree that you can't beat good old VHDL and SV (forget about Verilog).

To answer the OP's question, VHDL for design and VHDL/SystemC/PSL/FLI/Tcl for testbenches. I do try to keep up with SV as a good engineer needs to know both.

Regards, Hans

W dniu ?roda, 10 stycznia 2018 15:17:32 UTC+1 u?ytkownik john nap isa?:

hat may

= =

I use mainly VHDL (I often design complex data acquisition and processing s ystem and havily use VHDL records to describe complex data structures) I'm trying to use systemVerilog

BR, Wojtek

VHDL + VUnit

Regards, Lars

VHDL + VUnit

Regards, Lars

VHDL for design. VHDL + UVVM (Universal VHDL Verification Methodology, Open source) for verification

Using VHDL with a good testbench architecture and a good infrastructure library allows very efficient verification. BTW: UVVM also comes with open source BFMs (Bus Functional Models) and VVCs (VHDL Verification Components) for interfaces like AIX4-lite, AXI4-stream, Avalon MM, UART, I2C, SPI.

Same here. Even when not using OSVVM, I use VHDL primarly for my testbenches, sometimes with PSL when needed.