looking for systemC/TLM 2.0 courses

Hi everyone,

I apologize if this is maybe not the best audience for these kind of enquiries but I'll try anyhow.

I'm looking for a good SystemC/TLM 2.0 training course which is not too basic and can give me a head start for a real life project.

I'm not a black belt on C++ but I'm familiar with most of its concepts on top of C (which I use quite often instead). Since we have a budget for training in our company I'd like to make something useful out of it and given the current issues we are facing in architecting systems of increasingly complex features set, I believe that modeling would add value to our products and avoid many issues due to a wrong architecture.

Any ideas/suggestions?

p.s.: I've no problems to start some reading/testing by myself in order to fill the gap before attending the course.

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Reply to
alb
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I know it isn't what you asked for, and it is my personal opinion, but I recommend that you learn and use Verilog or VHDL instead.

This is the reason why. Hardware design is different from software.

OK, when I started with Verilog some years ago now, it was suggested that for someone used to C, Verilog was a better choice than VHDL. Verilog has enough similarity to C to make it easy to learn, but not so much that you forget that you are designing hardware.

You should be able to think in terms of wires and gates, even when writing continuous assignment statements and logic expressions.

You should be able to look at a logic schematic diagram and write HDL statements from it. You should not think in terms of sequential logic and C programs.

I don't have any actual recommendations for training courses in any HDL, but I am sure that they exist for Verilog and VHDL.

-- glen

Reply to
glen herrmannsfeldt

Hi Glen,

glen herrmannsfeldt wrote: []

I use VHDL since more than 10 years and even though I agree that learning to use it more efficiently is good, unfortunately is not top priority for the time being.

I do not want to do hardware design. I want to explore the type of architecture in order to give the go to the designers. On top of that an architecture may have several parameters (bus bandwidth, latencies, I/O throughput, etc.), therefore it is important to see 'easily' what is the impact on the architecture if we need to increase a value from A to B, will the overall design fall apart? Will the bandwidth be not sufficient, will it require too much memory?

I've learned to simulate my vhdl designs thinking in terms of transactions and I believe I can 'model' my system in behavioral vhdl, but I'm not sure is the most efficient way. We have embedded processors for which a behavioral model would be hard to replicate, while several of them are available in SystemC.

IMHO a modeling phase should not give the impression that we can generate the vhdl from the said model. The main idea is to verify that we are not going against a wall during the implementation phase because we didn't have enough margins.

A functional model should not have the low level details, but the transaction should be representative of the amount of data flow foreseen. A simple example would be the amount of traffic on the on board bus, every transfer should consider the amount of time it takes for the handshake on the bus, with timing values that match with the intended platform.

Ideally then, the model may cover more than just the FPGA functions and go up to board level and system level (more boards together). I couldn't care less if the board has all the necessary buffers to handle the speed we want, on the contrary I need to see, given a specified throughput what is the optimal bus size (8/16/32/64...). Power considerations may need to be added as well.

I believe learning verilog is too low in my priority list... (and will soon fall off the list!).

I want to get out of the wires and gates level. At least for the phase I'm interested in. /Polluting/ the architecturing phase with such level of details is risky and will inevitably blur the big picture.

[]

I know already a couple of courses for VHDL that I'm interested in, but unfortunately they are not in my current priority list (but they are still in the list!).

Al

Reply to
alb

I would definitely recommend the Doulos course, I have done their Comprehensive SystemC one and it was very good. The only disappointment was that we ran out of time so SCV, TLM and Synthesis were not properly looked at.

Good luck, Hans

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Reply to
HT-Lab

Hi Hans,

HT-Lab wrote: []

[]

I hoped you chimed in and knowing you recommend that course is a big reassurance. We are not so much interested in SCV or Synthesis but we are definitely interested in TLM.

There's a possibility that more people are interested in our site and we suddenly break through the right number to have them on site. I believe if that happens we can have a much more tailored course based on our needs and background.

Al

Reply to
alb

Hi alb,

if I may ask; where (which country) are you located? Have you ever attended another Doulos seminar? What is your experience? Especially with respect to UVM.

Hi Hans! Hope you are doing well.

Best regards Nikolaos Kavvadias

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Reply to
Nikolaos Kavvadias

I've followed several webinars but never a course. If I ever manage to convince my managers to send me to their courses I'll post a review, no worries! I live in Switzerland.

Al

Reply to
alb

Like Al, I also watch some seminars/webex' on the UVM and it gave me a headache so this is clearly something a 5 day training course would be ideal for.

Hi Nikolaos,

Yes thanks, I spend another great 2 weeks on one of your islands (Poros). Anybody who is fed up fighting FPGA, PCB, EDA tools I would highly recommend a quiet Greek island for a few weeks ;-)

Regards, Hans.

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Reply to
HT-Lab

Dear Hans,

Great! My brothers visited near-by sites this year: Hydra, Spetses (islands ) and Nafplion (mainland). Hydra and Spetses are quite close to Poros (clos est islands anyway). Historically speaking these tiny islands played a majo r part in the Greek Independence War (1821-1828).

I don't know much details; this band of brothers rarely meets in its entire ty these days: maybe once a year or every two years or so.

Nothing to add here ^_--

Best regards Nikolaos Kavvadias

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Reply to
Nikolaos Kavvadias

I used to work for Doulos, and teach SystemC and TML2 - we regularly ran courses at CERN, but normally VHDL and some Expert VHDL. Something makes me think you're based at CERN.

Since Hans did the course, the SCV content was relegated to an appendix. The main SystemC course included an introduction to TLM2, then there was a separate TLM2 course.

Knowing C++ is a definite advantage!

Have a look at the Doulos website, or email snipped-for-privacy@doulos.com,

regards Alan

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Alan Fitch
Reply to
Alan Fitch

I used to, has been a fun ride. Too bad I never got the chance to follow a course of yours. It seems now they are more and more pushing for SystemVerilog, while I lately was trying to fight my way with OSVVM which I find more appropriate for that type of community.

Uhm, 'knowing' is actually a bit vague, considering that I strongly believe that in order to 'know' a language it takes ~10 years of practice in the field! (I actually find this reading quite at the point:

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I did. BTW I found that A.L.S.E.

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provides the very same course from Doulos, are the instructors coming from Doulos or they are simply acting as a gateaway to Doulos courses?

Al

Reply to
alb

I'm afraid it's "the dead hand of the market"...

People who know C++ well, and who have some experience of VHDL or Verilog generally get on well with SystemC as "it's just another class library".

If you know VHDL/Verilog but don't know any object orientated language it can be "challenging" :-) However knowing Java (for instance) doesn't mean you know C++ of course (though can be quite helpful when learning SystemVerilog!).

The Doulos Comprehensive SystemC includes 2 days of C++ at the beginning, aimed at people who know C but not C++.

For on-site training the courses can be customised - but trying to compress the equivalent of 2 days C++ + 2 days SystemC + 3 days TLM2 can lead to peoples' brains metaphorically exploding.

ALSE have their own instructors. I remember they had one person up-to-scratch with SystemC. Generally they ran the courses in French. They use the same Doulos materials.

regards Alan

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Alan Fitch
Reply to
Alan Fitch

Hi Alan,

Perhaps a shrinking market for Doulos, however, it has been a growing market for us (including in UK).

What I do see in SystemVerilog's favor is the vendors are pushing the user community heavily to it since they can make more money with SystemVerilog licenses.

OTOH, recently we have had people switching from SystemVerilog to VHDL/OSVVM because their projects could not afford the pricing of a SystemVerilog simulator when OSVVM can do the same thing.

Cheers, Jim

Reply to
Jim Lewis

Hi Jim,

Jim Lewis wrote: []

This is one of our concerns as well. While the OSVVM seems covering the needs in terms of functionality, it still lacks the support needed in terms of verification IPs which may be a big plus (or minus).

Do you see anything coming soon on that side of the market or people using OSVVM will be forced to develop their own verification IPs?

Same here. Management won't provide the necessary means to go buying licenses for SV simulators and on top of that most of our team is hardware oriented. We actually proposed several training courses on OSVVM for next year budget hoping to get at least a couple (and I'm not included!).

Al

Reply to
alb

I just want to clarify that I left Doulos a year ago, and I have no knowledge of their current market. Also I didn't say that the VHDL market is shrinking. What I was trying to say is that there's more demand for SystemVerilog training than VHDL - but that doesn't mean that VHDL is necessarily shrinking.

regards

Alan

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Alan Fitch
Reply to
Alan Fitch

Hi Alan, ..

I guess using "the dead hand of the market" is not the most appropriate phrase for the leading FPGA design language.

I am not sure that is correct from what I understand VHDL is still the most popular Doulos language course, also if you look at the current schedule there are more VHDL than SystemVerilog courses.

I agree with Jim that the EDA industry seems to be doing its best to make this happen ;-)

Hope you are enjoying your new job and are allowed to use VHDL and SystemC,

Regards, Hans.

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Reply to
HT-Lab

------------------------------------------------- You may want to take a look on these simple systemc examples: My First systemC program systemC debug with SC_TIME Tip Simple multiplier and a test-bench in systemC ETHERNET packet scv RANDOMIZATION in systemC

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Reply to
93490

I recently studied the simple_bus example from systemc. It has not been converted to TLM, but still is a good example. To compile and run it, you may want to take a look at:

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Another issue that may interest you is SCV. It allows to write constraints in a system verilog style:

SCV_CONSTRAINT_CTOR(my_constraint) { SCV_CONSTRAINT ( a() * a() + b() * b() == c() * c()); SCV_CONSTRAINT( a() > 0 && b() > 0 ); } A simple example as well as makefile for compilation can be seen at:

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Reply to
93490

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