Well at first sight it is not indeed. But take into account the fact, that you have no hidden signal layers and related nightmares for errors to fix on the prototype board there (which does not save you the nightmares of misconnected power planes... so far I have had the only the latter, thankfully never to come true :-) ), then think that at the
6/4 mil rules you can do a lot of things (I forgot to mention it, I do 0.3 or 0.2mm drilling for vias/BGA pads), and it becomes a lot more attractive. Especially if you cannot afford a respin of the prototype (usually the case with me, and thanfully never needed one - although typically my second or third revision is 100% error free).Actually here is one prototype (recent shot of a 5-6 years old prototype, the CPU cooler got unstuck and I took the opportunity):
Routed using the same technique, not much free area left (especially if you count the 5 SDRAM chips on the bottom,
1 of which - the ECC - is routed but left empty).Dimiter
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