Gnd plane coupling with DDR routing from FPGA <-> DDR?

Well at first sight it is not indeed. But take into account the fact, that you have no hidden signal layers and related nightmares for errors to fix on the prototype board there (which does not save you the nightmares of misconnected power planes... so far I have had the only the latter, thankfully never to come true :-) ), then think that at the

6/4 mil rules you can do a lot of things (I forgot to mention it, I do 0.3 or 0.2mm drilling for vias/BGA pads), and it becomes a lot more attractive. Especially if you cannot afford a respin of the prototype (usually the case with me, and thanfully never needed one - although typically my second or third revision is 100% error free).

Actually here is one prototype (recent shot of a 5-6 years old prototype, the CPU cooler got unstuck and I took the opportunity):

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Routed using the same technique, not much free area left (especially if you count the 5 SDRAM chips on the bottom,

1 of which - the ECC - is routed but left empty).

Dimiter

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Reply to
Didi
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"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

The problem is determining what is 'good enough'. Putting planes (or even the voltage supply puddles and ground plane as Symon suggests) close together gets you a very low inductance pathway for delivering the power to the part. What your stackup had is widely separated power and ground which is not 'good', but depending on your needs might be 'good enough'. The other suggestion that someone posted to put the power/ground together in the middle accomplishes the same thing and saves you two layers at the cost of having fewer routing layers directly adjacent to the return plane. Whether that is enough or not depends very much on your particular design.

No. In fact to try to prove to the designer that it had to do with anything other than power (there was natural skepticism), I programmed the FPGA to simply toggle outputs every clock cycle and the failure condition would be when the internal phase locked loop lost lock so the only thing the PCB had to deliver was core voltage, I/O voltage and a single input clock that went into a PLL in the FPGA. He tried different 'filtering' on the PLL supply voltage, we played with I/O drive strengths and limiting certain pins to toggling at lower clock rates and it would always fail. The board only functioned somewhat when toggling all but a handful of I/O at a lower clock rate (1/4 of the higher speed ones). When the new board arrived, poof! suddenly all I/O could toggle at the full clock rate, could be driven at the full I/O current drive strength and not lose lock. The lowered inductance (impedance) in the power delivery network that comes with the better stackup was left as the only viable hypothesis for the failure. If you read Ritchey's book, you'll gain a better appreciation for the PCB's role in power delivery. The fundamental flaw that the designer I was working with had was treating the stackup as something only to connect all the points together and trying to minimize layers for cost reasons and being completely lost on what you need for good power delivery. The inductance/impedance in the path from the regulator to each load over the entire frequency range of interest is critical.

You're welcome. Good luck on your design. With a bit of thought and understanding about what is going on for delivering power and signal terminations and image return planes (which you seem to have a basic grasp on already) it should all work out just fine.

Kevin Jennings

Reply to
KJ

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

It's not so much the capacitance as it is the lowered inductance that the closely spaced planes brings you. Having a fire hydrant near a burning house doesn't help much if you only have a garden hose to deliver the water. The inductance of the power delivery network is the thing that delivers the power from the source to the load.

KJ

Reply to
KJ

We've found that a lot of cheap surface-mount crystal oscillators have a combination of sub-ns rise time and weak drive. So if they drive a few inches or more of trace, their output step can have a plateau right in the ballpark of Vcc/2, which is like hanging out a welcome sign for noise. The fpga clock inputs are very fast and have little or no hysteresis, so a tiny amount of crosstalk noise can result in multiple clockings on either edge.

CCLK can be a problem, too; we often buffer it with a Tiny Logic schmitt right at the fpga, especially if it's a shared SPI clock that goes everywhere.

John

Reply to
John Larkin

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

No, because everything is referenced to ground. My favorite stackups are:

12-layer S, G, S, S, G, P, P, G, S, S, G, S 14-layer microvia S, S, G, S, S, G, P, P, G, S, S, G, S, S 18-layer S, G, S, S, G, S, S, G, P, P, G, S, S, G, S, S, G, S 20-layer microvia S, S, G, S, S, G, S, S, G, P, P, G, S, S, G, S, S, G, S, S

S = Signal, G = Ground, P = Power. Microvias are laser-drilled vias going from the outside down just one layer - makes double-sided fan-out on high density boards much easier.

The advantages of these stackups are:

  1. All signal layers are referenced to a real ground plane.
  2. For normal board thicknesses (1.6 - 2.5 mm) it is easy to get 50-ohm single-ended and 100-ohm differential impedance on the inner signal layers with 4 mil track and gap (the outers give you about 42 ohms with 5 mil traces).
  3. You can use ZBC cores on the innermost power stack up achieve buried capacitance decoupling.
  4. You can split the power planes as much as you like without having to worry about signal integrity, because the splits are caged.
  5. You can adjust the thickness of the board by changing the prepreg between the two power layers without having any real effect on the electrical characteristics.

The possible disadvantages are:

  1. The via length down to the power planes will be longer than had the planes been closer to the surface, but this is unlikely to cause a problem.
  2. The board cost in increased somewhat over a six or eight layer one, but not by as much as you might think.
Reply to
David Spencer

It's not the frequency that matters, but rather the edge rate. It is the behavior of the edges that are altered by the characteristics of a transmission line. The frequency just indicates how often such edges occur. This is why many older designs fail when a manufacturer introduces a faster, die-shrunk, version of a part. Although the application is using the part in the same way, the unavoidable change in edge rate can break a previously working board.

Reply to
David Spencer

Of course so, I meant "120 MHz clock rate is nearly DC nowadays", I thought it was obvious from the context. It applies to the concrete DDRAM case allright.

Dimiter

Reply to
Didi

Hi KJ, This is a good analogy. I say the garden hose is between the planes and the FPGA. It matters not a jot if the planes had zero impedance, the BGA balls, and the vias to them, are the bottleneck that makes the plane capacitance moot. Cheers, Syms.

Reply to
Symon

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

Hi Nial, I doubt they press the 'autoroute' button on their PCB CAD tool! Cheers, Syms.

Reply to
Symon

Hi David, To be technically correct (the best kind of correct!) it's not the edge rate, but the rise time. :-) I'm sure that's what you meant, I'm just being pedantic... HTH, Syms.

Reply to
Symon

Or "fall time". ;)

The point I was trying to make (and which I'm still not sure Didi fully got) was that if a device is designed such that its outputs can operate at, say,

200 MHz, then running that device at 1 MHz will not generally magically improve the signal integrity.
Reply to
David Spencer

I got the point you made with your first post. In goes into details I explicitly did not want to go into, because one does not need to do it in this case, this is the essence of my point. It can be detailed as "at 120 MHz DDR clock frequency edges and generally related parts on the market are nearly as easy to use as if they were DC nowadays". I expected the "nowadays", put in context with the links to some board photos I provided, to make the point obvious enough. Clearly you do have to treat transmission lines as such, but no extra effort except keeping in mind you are doing that is necessary. I hope my point is now clear enough :-).

BTW, how many persons do you know who have designed boards of comparable complexity/density/speed to those I showed in the thread who would have a problem getting the point you made (which says it is not the frequency but the timing relationships which matter, put in a more general way)? .... :-) :-)

Dimiter

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In fact the denser board -

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- is routed by me 7 years ago, with 100 MHz SDRAMs at the photo.

Reply to
Didi

buried capacitance,

distance as possible

discrete decoupling caps

lower so the overall

It's not just the footprint under the bga that helps, it's the entire plane.

I sometimes add a few SMA connector footprints to pc boards, so I can TDR the power planes relative to the ground plane. It's amazing. A typical power plane, on an unloaded board, looks like a perfect capacitor to 20 GHz, with no evidence of reflections or edge effects. Then if you start adding bypass caps *anywhere*, it just looks like a bigger perfect capacitor.

I know one guy who doesn't use bypass caps at all, and his stuff works too.

John

Reply to
John Larkin

Hi John, As we've discussed before, I think that would be a really useful experiment if this thread was about microwave engineering (say). Sadly, we're talking about FPGA PDSs. FPGAs don't have SMA connections to hook up their power supplies to a board's planes, so, altough interesting, I think the TDR experiment results aren't applicable in this case. It doesn't matter how amazing the capacitance quality is, you can't wire it to the silicon. I still say, ditch the power planes, put the bypass caps (maybe X2Y types) on power puddles near the device, that'll work great. This save planes, which you can use as ground planes. This topology allows the designer to filter the supplies near the FPGA to isolate it. If you believe that your high speed signals work better with a return path, and I know some folk on CAF apparently don't, then when these signals swap reference from one ground plane to another you can just use a ground via for the return path as opposed to the situation where a signal switches from ground referred to power plane referred, which costs a bypass cap and two vias and has much more inductance. One thing from John's post I do find intriguing is his mate who doesn't use any bypass caps. I can quite believe that his stuff works just fine. I still think it's easier to get PDS right than wrong. Most designs will 'work'. That's why this subject is perfect for a usenet religious war! HTH, Syms.

p.s. From experience, I know John likes to read links I post so he can offer his reasoned critique. I saw the comment about 'bypass caps *anywhere*' in his post, and so I eagerly await John's response to this.

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:-)

Reply to
Symon

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

Hi Nial, I just re-read this bit, and would just like to clarify that it wasn't so much 'got away with' as 'had success with'! :-) It works out cheaper and performs better in terms of EMI, routability, SI over the whole board.

One more point, in the six layer stackup I suggested, I would make the centre core (between layers 3 and 4) thick, so that the signal layers

1,3,4,6 are close to their reference planes. There's some stuff in this link that explains why better than I can. (It's applicable for regular caps as well as X2Y ones!)
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Cheers, Syms.
Reply to
Symon

For FPGA designs with multiple syncronous fast IOs?

Nial

Reply to
Nial Stewart

power puddles near

planes. This

it. If you believe

folk on CAF

to another you can

signal switches from

and has much more

Symon,

You've posted useful snapshots of board desing before (ie to illustrate the usefulness of micro-vias).

Any change of a screen shot of a board you've done using this technique to illustrate things better?

We have an interrupted power plane with is _really_ well decoupled at the FPGA and DDR so our current thinking is to use routinh on layers 1 3 and 6.

From another post...

core (between layers

planes. There's

for regular caps as

Hmm, more expense specifying stack build up?

I think a 'normal' 6 layer stack uses relatively thick cores with thinner pre-preg so layers 3 and 4 end up significantly nearer the planes at 2 and

5 that the top and bottom layer.

Bearing this in mind, if we're using a normal stack perhaps we should be using the top and layers 3 and 4 to route out to the DDR.

Or again I'm worrying about things too much?

Hopefully.

[panto] Oh no it's not [/panto].

Nial.

Reply to
Nial Stewart

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

I'll have to ask my client if it's ok.

So, just to be clear, how are you planning on connecting all your supplies? Vccint, Vcco for each bank, Vccaux, to use the Xilinx names. Do you have different voltages on some Vcco banks? I usually have 3.3 and 2.5 volt banks. Cheers, Syms.

Reply to
Symon

His footprints make no sense to me. Why three pads and six vias for one bypass cap? Is an X2Y cap something nonstandard?

Yes, most bypass schemes work, which is why so many people have such different opinions.

John

Reply to
John Larkin

Don't know what he's doing lately. Last time I visited him, he was doing big boards with a lot of msi and ecl logic.

Most FPGA designs use "high frequency" power, in that there's not much low frequency component to the supply currents. Contrast this to a CPU that may go from low power to 100 watts in nanoseconds.

Close power:ground planes are great at furnishing current into high-frequency loads. Bypass caps furnish the brute charge storage that keeps the rails stiff at lower frequencies, if there are any.

Our fpga-type boards use a single ground plane (even for mixed analog/digital stuff) and typically two split power planes. We usually use four bypass caps per voltage per fpga, 0.33 uF 0603 typically. We don't distinguish "reference planes", but assume any plane or pour is at AC ground. We don't worry about logic signal traces crossing pour boundaries or changing "reference" planes. We may worry about very low-level analog signals riding over a power pour that could be noisy... we're talking microvolts here.

Certainly more complex stuff - multiple ground planes, zillions of mixed-value bypass caps, extra vias to "supply return currents" will work too.

John

Reply to
John Larkin

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