clock generation with DOPPLER shift

Build a phase accumulator, and use the MSB as your clock. This is an accumulator that runs at a much faster rate than the clock you are generating, you control the frequency of its output by setting the input phase increment. In you case, create the doppler by varying the phase input value.

Regards,

John McCaskill

Direct Digital Synthesis (a.k.a. phase accumulator) can generate the desired average frequency, but at excesive and unacceptable jitter. Assume a 500 MHz accumulator clock: It will generate more than 1 ns of jitter.

Let's look at the desired frequency shift in the time domain,

1 MHz = 1 microsecond = 1,000,000 picoseconds 1 MHz - 5 Hz = 1,000,005 picoseconds.

That means, the clock period of 1 microsecond must be nudged gently in steps that are much smaller than 5 picoseconds.So we are talking femtoseconds here. I do not see how this can be done with purely digital means.

I could imagine a 5 Hz linear ramp added to the 1 MHz clock, so that the input threshold moves the frequency in the desired way, but you are still facing random noise and unavoidable jitter. I think our analog friend are better at this. They play with modulators and crystal filters, and are more comfortable in the frequency domain. Digital circuits work inherently in the time domain. There may even be a mechanical solution (something spinning at 5 Hz)... Maybe someone else has more constructive thoughts.

Peter Alfke

Direct Digital Synthesis (a.k.a. phase accumulator) can generate the desired average frequency, but at excesive and unacceptable jitter. Assume a 500 MHz accumulator clock: It will generate more than 1 ns of jitter.

Let's look at the desired frequency shift in the time domain,

1 MHz = 1 microsecond = 1,000,000 picoseconds 1 MHz - 5 Hz = 1,000,005 picoseconds.

That means, the clock period of 1 microsecond must be nudged gently in steps that are much smaller than 5 picoseconds.So we are talking femtoseconds here. I do not see how this can be done with purely digital means.

I could imagine a 5 Hz linear ramp added to the 1 MHz clock, so that the input threshold moves the frequency in the desired way, but you are still facing random noise and unavoidable jitter. I think our analog friend are better at this. They play with modulators and crystal filters, and are more comfortable in the frequency domain. Digital circuits work inherently in the time domain. There may even be a mechanical solution (something spinning at 5 Hz)... Maybe someone else has more constructive thoughts.

Peter Alfke

Hi Peter, John and all others !

Thanks a lot for your answers!

In analog technics, I already thought of using a VCTCXO with the desired amount of frequency variation, driven by a DAC !

But if there are other pure digital methods: please keep on posting them !

Thanks, bye BEN

Peter Alfke wrote:

That is your best approach. The FPGA can verify the frequency, by Freq Ctr, if you wish, and simple PWM/PDM DACs can be made in the FPGA, if the dF precision is not large : it probably is not, 5Hz is 5ppm, so you are unlikely to want that to be 5.000ppm/4.999ppm etc Using an external VCTXO will also give you a truly walking phase, with no steps, which is probably more usefull.

-jg

Ben, Write a clock divider having the divider as input signal (and not as generic parameter). ==> in this divider, u count clk cycles , when count reaches divider, u toggle divided clock once again the divider is an input signal ( be careful to register it on clk falling edge to avoid pbs...)

F' = F / (2*(1+k)) where k is the divider if you have say F=48 MHZ , k = 23 gives you a 1.00 MHz clock , k = 22 a

1.0435 Mhz , k=24 a 0.96 Mhz clk etc... ....k=24e6 --> F'= 1Hz....

Jerome, Ben wants to change the clock in smaller increments than 1 ppm (I suppose something like 0.1 ppm, which gives him 50 steps up from nominal 1 MHz, and 50 steps down from 1 MHz.) I see no way to achieve that with digital divider stages from a

Ben,

if you can afford to use a small amount of analogue circuitry around your fpga, i suggest you use a second 1000010.0 Hz oscillator (this can be a "detuned" 1 MHz oscillator) and mix the received signal with this this oscillator down to the audio domain using a double balanced mixer. A lowpass filter (or better a so called diplexer) must be used at the IF port of the mixer.

The frequency variation in the downmixed signal stays the same, so with this arrangement you have shifted the scenario from 1 MHz, where a 5 Hz variation is a difficult to detect 5*10E-6 effect to a 10 Hz audio signal where 5 Hz variation is a easy to detect 50 % effect. This scheme is the usual one for comparing ultra stable oscillators against each other, where variations smaller by some orders of magnitude have to be measured.

No matter what scheme you will use: Keep in mind that a "normal" x-tal oscillator has a tempco of app. 1*10E-6/K. So a normal x-tal oscillator will give you a 1 Hz variation per Kelvin @ 1MHz, well in the region of the Doppler that you want to measure. This is a indication that a "better" oscillator has to be used. Don't go for a TCXO, look out for a cheap OCXO.

Rgegards

Ulrich Bangert

"Ben Marpe" schrieb im Newsbeitrag news: snipped-for-privacy@z14g2000cwz.googlegroups.com...

OF COURSE, use an ordinary XTAL and control its temperature with the FPGA. Perhaps some pins driving resistors stuck to the XTAL case? Some other pin driving a servo controlled can of freezer spray? If Ulrich's figures are correct, +/- 5K gets you what you want! :-) Cheers, Syms.

Great,

thanks a lot for all your answers !

I'll try to downmix the analogue VCXO signal...

Bye, BEN

Ulrich Bangert wrote: