Dear experts in this newsgroup,
in my diploma thesis i'm using a FPGA for baseband signal generation. I'm interested in generating and varying a clock of 1Mhz which is DOPPLER shifted +/- 5Hz due to movements between receiver and transmitter.
The +/- 5Hz Doppler must be applied in a very "smooth" way, the step resolution should be as fine as possible.
Any ideas how to do this on a (Xilinx) FPGA ? The sine output of Xilinx LogiCore DDS isn't necessary and the step resolution might be even a little bit finer for my application.
Thanks a lot for every single hint you can give to me !
Greetings, BEN