FPGA with 5V and PLCC package

The abstraction of the logic doesn't matter in the sense of a truth table (as long as it is complete). The result will match the truth table for sure. But, the actual logic pathways will not bear any resemblence to the schematics, and so the timing will be radically different than what is drawn. Of course, with good logic design, it will still meet the design spec, but with crummy design planning, it sure won't.

Jon

I think Herbert was using the time, to illustrate the need for schematic flow, and built might not have meant physically assemble a PCB, but probably includes bitstream and prom generate.

You are both right - Herbert has a very short time or this section of the course, and yes, full VHDL Xilinx tool flows, will have too long a learning curve.

His ideal is to continue to run the old Viewlogic system, and I think some posts offered some hope.

Failing that, I've suggested a Boolean Eqn entry scheme, that does have a shorter learning curve, and is quick to run - and that is close enough to the gate-level to see the AND.OR.Registers

I have one ToolChain here, on a Flash drive, in under 10MB.

-jg

Then this fantasy has become true since many years. This is a 12 week lecture about computer organization an we have 45 min time every week for exercises. We have combined this time to 3 x 3 hours to reduce overhead. The first

3 hours are mostly needed to explain and discuss the processor architecture and to get familiar with the VIELOGIC system. So there only 6 hours left to implement and test the CPU (some groups need a few additional hours, but they are willing to spend this extra time because most of them are really interested). They don't have to start from zero, the design is given at block level, but all the gates and flip-flops they have to insert and wire themselves. And this is not a 1-bit CPU, but a 16 bit processor (which can address 64 kbyte external memory) with external interrupt support and built-in IO (8 input and 8 output lines).

The board already exists, all they have to do is to generate the bitstream to download. (I have posted a link to the description of the course in the OP, the documentation the students get is: ftp://137.193.64.130/pub/mproz/mproz_ub.pdf ).

Yes, but the actual software doesn't support this chips anymore. We also could go back to the last version which supports XC3000 so we could use the current hardware. But I'm not even sure whether this version runs in XP. If we have to make a cut and drop the old system, then we don't want to replace it with something which also isn't supported anymore.

I would like to use an actual system which we could use for the next

8-10 years without modification (like we did with VIELOGIC/XC3000). But maybe we have to drop the hardware completely and finish the course after the simulation. But it was always a big motivation for the students to finally seE the processor running on a simple PCP board with nothing than an FPGA, EPROM, SRAM and a few LED's.

Hebert,

As a recent student myself (been doing FPGA design for 2 years now) I've gotta say.... HDL.

Actual FPGA design flow, in the real world, is

Preliminary Design - Block Diagrams Detailed Desgin - HDL Verification - HDL

In terms of getting an idea of how many flops and gates (you said they should be able to get an idea for the scale of the design) all you have to do is not allow them to use high level constructs.

A > taught design methods on design tools and FPGA parts that most folks on this