How to add some SDRAM to a FPGA board ?

Hello,

I thought that I could ask for advices on this group since most high-end embedded CPU have the same constraints.

I would like to add a good RAM capacity to existing evaluation/development boards equiped with 2.54mm pins. Ideally that would mean 32 or 64MB with a 16-bit datapath (32-bit would be too wide, too many wires...). SRAM are not possible, the largest I have are 36Mbits in BGA, this is not suitable for a first prototype. And using/hacking a SODIMM is not suitable either because they are 64-bit wide.

I also have SDRAM chips that fit the description, like PC133 compatible 256Mbits SSOP with 8-bit or 16-bit wide bus. However, I don't feel like making a PCB for just 1 or 2 chips. There is still the old hack of wiring the pins with fine wires but the chips are very fine pitch (.65mm) and it's going to be difficult...

Is there another method ?

Oh, and once the chips are wired (a pair of 256Mb will give 64M bytes), how does one initialises and uses these complex beasts ?

yg

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Reply to
whygee
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I'm afraid you're not going to be able to (easily) achieve what you want.

First off, you'd need to clock the SDRAM with the output of a PLL, so that you can control the skew wrt the control/data lines. Also, with a 133MHz clock you need to match trace length/impedence on all the pins from FPGA to SDRAM. That just ain't going to happen with a 'old hack [job]'.

You also need an SDRAM controller inside the FPGA, parameterised to your particular SDRAM chips.

You need to find yourself an eval board with SDRAM already.

Regards,

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Reply to
Mark McDougall

Alternatively, you could find some other high-density (non synchronous?) memory technology... not up on these sorry. Anyone else?

Regards,

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Reply to
Mark McDougall

The best I have is 4MB of static RAM, which is already large (and some room too, with two DIP40 packages, and time, since it's 70ns access time) but won't buffer enough data...

thanks,

yg

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Reply to
whygee

That's what I thought...

I think that it is possible with the FPGA that I use (Actel ProASIC3), I have spotted functionalities of the IO pads that ease these designs. They have things like programmable delays and skews to avoid driver contention on bidirectional buses for example.

hmmmm If I cut a bunch of same-length wires, a la Cray-1, that could maybe help... (kidding)

Fortunately, the eval boards have rather short traces to the headers so impedence will not be a big problem (I hope).

Also my designs don't clock faster than 100MHz, and I thought that it's possible to downclock SDRAM chips, provided the cycles are adjusted.

Sure, I'm looking at datasheets and VHDL "cores" too.

Should this discussion continue on comp.arch.fpga ?

I have one that has what looks like a SODIMM socket, but it's an Altera thing for which I have no programming cable or software suite :-/

Furthermore, I believe that since I'll have to use SDRAM anyway one day, then I should hit the bullet and go forward.

thanks,

yg

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Reply to
whygee

A

You will not need to match lengths at 133 MHz that much, 10-20 mm won't make any difference (just do the math).

However, not having a ground plane to reference the signals to may well become an issue.

Since this is a one-off thing (I suppose you do not intend to hand- wire them DDRAMs in mass-production :-) ), you may be better off if you explore and cut a piece (literally) from a DDRAM DIMM, some do use DDRAMs with 16 bits of data (this means you can have 32 or 64M maximum depending on which parts you use). Now how you connect this piece of board to the other still remains unclear, of course; using many evenly spread GND wires between the two might help, but you won't know if it will work until it works...

Dimiter

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Reply to
Didi

t.

hat

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Have you considered a different family? There is a $40 Xilinx eval board available from Avnet. But it still does not have ram. That will likely be a $200 or higher board.

A

The only hard part is the wiring. A decoupling cap will need to be wired directly between the power and ground pins. Actually, this may be a show stopper. The low impedance of the ground plane and its capacitance helps a lot to reduce the high freq spikes on the power bus. By wiring power it is possible to add too much inductance and the cap may not be able to provide a low enough impedance.

As long as your wires are very short (both on board and off board), less than 2" for example, the SI and clock timing will not be significant issues. To mitigate the output delays on the FPGA you should register all signals in the IOBs.

That will work. You can clock an SDRAM as slow as you want to some point. You do have to provide a periodic refresh cycle unless you are doing that in software. But the clock speed won't have much to do with the SI and power decoupling issues.

r

That would be a good venue. I have not found a good venue for discussing FPGA CPU cores. If you are interested in MISC processors, comp.lang.forth is a good place.

You can get the Altera softare for free just like the Xilinx software. The programming cable is not a lot of money. I would bite the bullet and use that for a first pass. Wiring an SDRAM chip is likely to delay you some considerable time.

Rick

Reply to
rickman

... snip ...

To evaluate the effects of wire length, consider that 1 foot (1/3 meter) of wire represents about 1 nS in a vacuum. Probably closer to 2 nS in your environment. 100 MHz chips are cycling in no more than 10 nS.

Also bear in mind that you have to provide the appropriate signals and addresses to refresh the memory at some interval. See the data sheets for this. The circuitry is a complication, not present in static memory chips. The variation in delays through this circuitry also need to get absorbed in that 10 nS window.

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Reply to
CBFalconer

There are 10 to 20ns sram in TSOP, and faster if you pay more. 16 chips in a small PCB is not impractical. Not using PCB at all is impractical.

Reply to
linnix

As long as the trace lengths from the FPGA to the expansion header are also taken into account...

Regards,

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Reply to
Mark McDougall

there is indeed some inevitable variation on the board, like 10 or 15mm between min and max length (i'll have to measure). And i'll take this into account obviously.

However I guess that i'll have many problems from other domains before hitting the speed barrier :-) Fortunately, I have a bunch of new 48LC16M16A2 chips and they seem to be widely used. I think that the ACME Fox uses it and I once downloaded the initialisation sequence once... Still, I'm not confident.

thanks for the hints, yg

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Reply to
whygee

I know these, but in the end it's too expensive... even for a proto.

it is, for two reasons : price and bus load.

I have bought 8ns chips to upgrade the 12ns parts of my ACME boards (see

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) and they are only 512KB each. And even 12ns is not cheap. And 16 such chips is not enough capacity.

Furthermore, putting 16 chips on the same bus will void their high speed, since the capacitive load on the pins will go beyond reasonable. [in a not so distant youth, i tried to make a high-speed SRAM bank made out of

32KB cache SRAMs from scrapped computers, but the bus loading and the power dissipation cancelled the idea before I started to implement it]

And finally, I already have small high-speed SRAMs, the SDRAM is more for "storage" and the access speed is not an issue ( Not using PCB at all is impractical. hmmm... I could sacrifice 2 or 3 SDRAM chips, and i have already soldered weird things. So that is still the "easiest" solution before making a custom board. I don't have suitable proto boards either.

Broke, weird and lazy is a dangerous combination :-)

yg

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Reply to
whygee

Yes but other issues arise. And I've read everywhere that SDRAMs are difficult to use... getting pas initialisation is often described as ... a lot of work.

that's what bothers me most. I'll check if there is an auto-refresh mode that cuts my efforts.

Also : If I scan the buffers sequentially at a known rate (this is for audio samples) then I could arrange the interleaving in such a way that no explicit refresh is needed.

I suspect that this method is used in video adapters, since at least one old personal computer (a french 6809-based thing popular around 1984) uses this idea. So I will try to combine both refresh and normal scan...

Static RAMs also have their gotchas...

Certainly. Correct data latching is necessary.

Damn, I'm almost afraid of what I've got myself into...

regards, yg

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Reply to
whygee

I read a little bit of your web pages. You are using it for code storage, right? Why can't you use flash?

Reply to
linnix

In message , CBFalconer writes

SDRAM requires initialisation during power-up with different signalling patterns to regular RAS-CAS access. The manufacturer's data sheets will give you the gory details -- it's not easy and I'm not sure it can be implemented through software and a simple address/data bus interface from a microcontroller. At least you might have to add a dedicated SDRAM controller chip. An embedded system I worked on added 1-2 Mb of SDRAM to a cell-8051 but there was a lot of dedicated silicon to make the SDRAM run.

Static RAM, although more expensive, is going to be easier to add to a test/dev system if you want more memory. It can also be remotely probed (stop the CPU, force the /WR line high then read off the memory contents in dual-port mode. Great for single-step debugging).

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Reply to
Robert Sneddon

... snip ...

If for audio why in the world do you need such high speed chips?

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Reply to
CBFalconer

well, * I just happen to have a small ribbon (90-ish) of 48LC16M16 that match the speed of my computation core (I stick to 100MHz pipelines) * Whenever I downscale a project, I always end up bitten by the speed demons (ouch) * sound processing, effects, synthesis and whatnot consume so much computational power that, well, I'm not even sure that the A3P1000 will be enough for some of my friends like Satine

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who use severa laptop on stage but are annoyed by the necessity of using Windows there. * Any headroom or margin is eaten in some way in SW... * In fact I have no idea of what I'll end up doing, so "high speed chips" is questionable with this perspective, if the workload is not yet characterised ;-) * what's wrong with high speed ? :-) * etc.

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Reply to
whygee

The SDRAM thing just popped up on the surface of my brain since I realised that some DSP/sound applications (that I resurrected) need a lot of volatile storage. Like maybe one minute of sound samples or things like that. The program/code can fit is smaller, faster SRAM.

Hope this is clearer now,

yg

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http://ygdes.com / http://yasep.org
Reply to
whygee

A thick copper wire will do the trick... I even have some copper sticky tape if needed.

Who know if there is ever going to be a production ? :-)

I have a bunch of SDRAM DIMMs but they are a bit... complex. also, tracing where each pin goes to which pad is going to be... tedious. it's probably not less complex than soldering directly to the pins... (except for the size but I have one or two ideas)

I won't risk the FPGA board, i'll use 2.54mm connectors. If something goes wrong with the FPGA, or if modifications are needed, i'll just unplug.

sure :-)

hmmmmm I slowly realise that it's obviously weird, but not impossible ... I think that I've seen worse, maybe at

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and other places. I just want to get the SDRAM pins, functions, timings and sequences right before I spend time making a (proto) PCB...

regards,

yg

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http://ygdes.com / http://yasep.org
Reply to
whygee

Yes, they all have auto refresh, but it does require you to create the refresh cycle, the SDRAM provides the address using an internal counter. I don't remember the details, but the refresh cycle is just like a RAS cycle, IIRC, it just has a different signal asserted.

Have you looked for IP anywhere? opencores.org may have an SDRAM controller.

If it is not easy, don't bother. It can make your design more complex than needed. The refresh cycle is very simple and only takes one clock cycle every 15 us I think.

Reply to
rickman

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