FPGA decoupling calculation

A worthwhile analysis would begin with knowing the current waveforms that the fpga pulls on its various supplies. That would then be dumped into the measured or estimated impedance of the bypassed power pours. Does such current waveform info exist for your part, in your application? If not, it's back to thumps.

I wonder if anyone here has encountered a situation where an fpga failed because of inadequate bypassing. I've done dozens of Actel, Lattice, and Xilinx apps, including mixed-signal stuff and picosecond-jitter things, and I've never had a problem, even as I keep ratcheting down on bypassing. So I don't understand why so much is made over this issue.

John

Has anybody tried writing nasty test code?

My straw man would toggle a lot of FFs for X cycles, then do nothing for X cycles. Loop. Scan through various X to see what happens.

Many years ago, there was a whole branch of hardware geeks that did nothing but write memory tests. I wonder if that sort of technology would be useful for FPGAs.

Hal Murray schrieb:

I did quite some time ago.

Try again some time later, ist just a cheap (free) account with 4MB/hour and I just blew it :-0

Regards Falk

Hal Murray schrieb:

OK, its available again.

Regards Falk

Not sure why doing nothing for X cycles is of any use.

It's fairly simple (and useful) to write code for something that simply toggles every output pin on every clock and put each of those outputs at the end of a long shift register so that internal flops in the device get used as well. Run it at different clock speeds, if it's suits your needs. Been there, done that....it's a good stress test.

KJ

KJ schrieb:

To measure the broadband step response of your power supply network.

It ist NOT enough!

Regards Falk

I was trying to draw current at a lower frequency. Adjusting X changes the frequency of the load.

Toggling everything would take the most current, but it the on chip caps work well the rest of the system will see a nice simple DC load. Waiting half the time will only draw half as much current but at a lower frequency that the power supply might not like.

Broadband step response is not terribly useful, you want to know what the impedance is across the entire frequency band that the part can draw power from. Sweeping the clock frequency with a design that toggles everything and measuring supply voltage dips and looking for functional upsets is more strenuous.

It's much more than a step response.

KJ

OK, but so does simply changing the clock frequency. Sweeping the clock frequency from DC to light will gather the information.

I doubt that it would be a DC load. Those on chip caps get their charge from the caps on the PCB through the PCB impedance. Those caps in turn get their charge from other caps and PCB impedance and on back to the regulator. None of that will make the chip look like a DC load. In fact if it did look like a DC load then one wouldn't need to supply any capacitors on the board since the regulator can certainly supply the current demands of a DC load.

No, the amount of current is only 'half' in some overall global measurement of power draw. The chip needs to be supplied with the instantaneous current that it demands to operate (otherwise it will fail functionally). The instantaneous power demand of the part when it does make it's demand after waiting is the same as if you hadn't waited at all. If it suddenly needs an extra 1A on 'this' clock cycle, it won't matter that the last time it needed the 1A was the previous clock cycle or if it was 'X' clock cycles ago...that is until you get up to the point where the part is on the verge of failing because the power distribution network of the entire system can not supply the dynamic power quickly enough (which is what you're testing to try to find).

KJ

KJ schrieb:

I think so. You can do a fourier transformation to convert the step resonse into the freqeuncy domain.

Iam afraid you are mixing this up with a frequency sweep using a SINE wave signal, as you would do whn you measure a filter or something. But a clock with variable frequency is NOT a sine wave. So the behaviour is different. If you do continous toggling at different freqeuncies, your voltage regulator will not be challenged, since it has only to supply a constant current. Similar for low frequency caps. Only a burst signal will stress ALL components. Read the link and think about it.

OK, my fault. I mean a step resonse to a burst signal.

Regards Falk

What you're interested in is knowing what the effective source impedance of the power supply network is across the entire frequency band of interest (DC to light). Step response doesn't really do that very well.

Not at all. Those toggling flip flops are all squarish waves and each of them toggling presents a whole slew of harmonics to the entire power supply system.

Nope, not DC....but your PCB/caps do need to be designed adequately so that the regulator is only being called on to supply current over a relatively small frequency range since the output inductance that it presents will prevent it from supplying any high frequency current. Maybe you're missing that when I say to sweep the clock frequency I'm not meaning just somewhere around the operating point but all the way from DC up to as high as you can go with the part.

Again, every toggling output is a squarish wave and the chip will be making demands for current over a broad frequency range, regardless.

Kj

A gated clock would be a severe bypassing test, since the "DC" current draw would jump as the clock started and stopped, which would stress the low-frequency transient response of the caps and the regulators. This could easily be a bigger hazard than the GHz stuff.

We've recently done some gated clock things, with switching supplies, without problems. A lot of bulk low-esr capacitance is a good idea here, if your regulator stays stable.

John

Burst clocking will generate, potentially, amps of low-frequency transient loading on the power supply. Slowing down a constant clock will not have that effect, since the average Vcc current will fall as the clock frequency falls.

This current waveform...

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is a heap different from this one:

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John