The scope of the subject and the possible implementations are too large to answer your question.
Since it *appears* from your posts that you want to use the FIR for real-time processing, the most straightforward implementation is a fully parallel FIR filter which takes in 1 sample per clock and performs a multitude of operations in parallel during each clock, delivering the filtered output many clocks after the last input sample is clocked into the circuit. The latency is a function of how the FIR is implemented and what level of pipelining is used to increase the possible process speed.
The cutoff frequency is a function of your FIR. FIR filters with fewer taps have poorer characteristics in things like passband flatness, stopband attenuation, and the steepness of the cutoff than longer filters. ARE YOU FAMILIAR WITH THESE PARAMETERS? It seems that all you're thinking about is "cutoff" with no regard for what a filter really entails.
You MUST do your homework - as in "basic research" - before you can take on this task. We cannot feed you piecemeal answers when it appears you don't have the fundamentals down.
Sorry, I mixed up the words ;) here's the correct one...
You have a clock frequency Fclock. And a sample frequency Fsample.
Suppose your impulse response length is N taps.
If Fclock =3D N * Fsample this is simple.
Every N periods of Fclock it receives a sample. Then, N times, it takes a coefficient, and multiplies it with the =
appropriate sample of the input :
sum of Coeff(n) * Input(T-n) for n in [0,1 ... N-1]
So it takes N clocks to process a sample because you use 1 multiplier a= nd =
you have N taps.
Now if you use N multipliers you can process everything in one clock an= d =
therefore use Fclock =3D Fsample. But you are going to use much more sli= ces =
in your FPGA.
And if you have Fclock =3D N * X * Fsample
Then your filter is faster than what you need, but that is not a proble= m, =
once an input sample is processed, it will just sit idle waiting for the= =
next input sample. In this case you could process X channels instead of 1 channel still =
using 1 multiplier, by using the time the silicon is idle to process the= =
other channels.
Get it ?
Not necessarily ;)
An impulse response is just a list of numbers. It does not have a cutof= f =
frequency. If it is a filter all it can have is a cutoff frequency ratio= =
which is a number without a Unit (no hertz, just a number), for instance= r =
=3D 0.1 for a lowpass filter. Only when you say "the sample rate is Fs" then you can say "the cutoff = of =
this impulse response when used on a signal of frequency Fs is r * Fs" o= r =
0.1 Fs in this case.
If you change the Fs it will just scale.
Now if your processing is not done in real time, say for instance you =
sample a chunk of data at Fs then you store the data in a buffer then yo= u =
stop sampling and you take the time to filter it, you can use any clock = =
you want since it's not in real time anymore.
No, you should set the clock frequency so that it's practical for you.
Say your Fsample is 1 MHz you have N =3D 10 taps in your filter for each sample you need 10 multiplications and 10 additions it takes a clock cycle to do a multiply + accumulate
So you need a Fsample * N =3D 10 MHz clock at least.
But if you have other stuff in the FPGA running at 50 MHz you can use 5=
0 =
MHz instead. The filter will just sleep during 40 clock cycles then work for 10 cycl= es =
then sleep again etc.
Well I have bad news for you lol. Since the multipliers in your FPGA don't reach that frequency you will = =
need to use several multipliers and adders in parallel. For instance if you have 10 taps and 600 MHz you need 6 billion MACs/s = =
and if your multipliers run at 100 MHz (for example) each provides 100 =
million MAC/s so you're going to need 60 multipliers and a spaghetti =
monster of logic.
And since the FPGA fabric doesn't run at 600 MHz (unless you're rich) =
you'll need to input several samples in parallel and add still more =
spaghetti logic to coordinate all this stuff.
What is the signal you want to filter ? Who chose the sample frequency ? Is it a REAL application which NEEDS that speed IN REAL TIME ? If it is= , =
it is going to be very EXPENSIVE. What is it that you want to do ?
I am planning to support 256-taps with direct form FIR filter which suffers from less speed and more hardware resources compared to distributed arithmetic architecture( i dont know about this)
I have tested my design with inputs as impulse test,step test,sine,square,sawtooth,pulse and white noise...I dont know how to check for overflow?wat is the test case?
I am planning to support 256-taps with direct form FIR filter which suffers from less speed and more hardware resources compared to distributed arithmetic architecture( i dont know about this)
I have tested my design with inputs as impulse test,step test,sine,square,sawtooth,pulse and white noise...I dont know how to check for overflow?wat is the test case?
"I read somewhere that I could." "I want to build an 8-channel, 16-band graphic equalizer for my home theater." "To make a brick wall filter for my sub-woofer." "To disguise my voice when I call co-workers in the middle of the night." "I love karaoke."
In any case, the background and specifics fill multiple chapters in textbooks. I don't expect anyone can condense it down into a digestible newsgroup message for you. The best you'll get is a reading list. Google is your friend there.
I have tested my design with inputs as impulse test,step test,sine,square,sawtooth,pulse and white noise...I dont know how to check for overflow?wat is the test case?
====== Quantization effects is a whole chapter in itself.
Dear faza, You're starting to get slightly irritating now. This won't help you get answers to your queries. A lot of folks on this newsgroup are willing and able to help people just starting out in the field, but, like God, they like to help those who help themselves.
Take your latest post.
Why don't you STW before posting? Googling for FIR filter implemented in real time gets nearly 10^6 hits.
It may also further your education to read this:-
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Please pay particular attention to the section:-
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Spelling 'what' as 'wat' apparently "makes you look like a semi-literate boob" to save one entire keystroke, especially as you piss away the saving by using three question marks when one will do just fine.
Finally, here are some feebie DSP books,
formatting link
this site
formatting link
has at least two app notes about FIR filters in FPGAs,
and this site
formatting link
is for when you become more experienced.
Now, be a good chap, and go do some reading. HTH., Syms.
Ironically, it is precisely that which keeps me from writing him off completely. There's an outside chance he's some jr. high school kid feeling his way into the deep end. But, as you say, I'm still waiting for the right questions.
OTOH, (you knew this was coming!) I see you are relatively new here, and I'd be delighted to be told of someone who started off on this newsgroup as 'slightly irritating' and progressed as far as being 'not quite as irritating as you used to be'. In my sad middle aged cynicism, even the usenet nutters aren't what they used to be!
I am facing problem while synthesis of Fixed point data type.I cannot change the synthesis tool.Is there any method which can convert fixed point to integer before hand and perform computation and convert back to fixed point without affecting the precision.?
In my FIR filter design i will sample the input and perform computation,produce result with control signal and then i will sample the next data..ultimately i will waiting for the o/p control signal before sampling the data..now my question is how this logic will be implemented as hardware..do i need to store my input samples in ROM or i should depend on the software to do this?
I am facing problem while synthesis of Fixed point data type.I cannot change the synthesis tool.Is there any method which can convert fixed point to integer before hand and perform computation and convert back to fixed point without affecting the precision.?
In my FIR filter design i will sample the input and perform computation,produce result with control signal and then i will sample the next data..ultimately i will waiting for the o/p control signal before sampling the data..now my question is how this logic will be implemented as hardware..do i need to store my input samples in ROM or i should depend on the software to do this?
pls clarify.
regards, faz
Dude .. give us some background ..
Are you a student? What year? Is this a project or an assignment?
I presume you mean fixed point with the binary point not immediately to the right of the least significant bit, sometimes called scaled fixed point.
Adding such numbers with the same scale factor is the same as adding integers. Multiplying follows the rules you learned in 3rd grade, the digits (bits) after the binary point of the product is the sum of the bits after the binary points of the to operands. Multiply should give you a double length product, select the appropriate bits.
I want to know which is the right way of implementing the hardware(industry standard)..I have referred various FIR implementations where they are mostly handling filter coefficients as integer(truncating from fixed or floating point using MATLAB) or binary.Is it difficult to handle and implement real(fraction) filter coefficients value directly in the hardware?
for example:
Filter coefficients:
fixed point=3D0.081207275390625 or signed integer=3D 6945 or fixed point binary =3D0011011001000010
all the above are equivalent but belongs to different data type..Now i am confused which to select for implementation in my code..
Note:
Fixed point representation is looking challenging for some synthesis tool as it not supported. Signed integer looks simple but less accurate Fixed point binary looks tedious..
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