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Favourite Design Entry Optomisation Method?

I'm a hardware design engineer with 10years background in FPGA design. To date all my design entry and simulation has been with VHDL but I seem to keep having to type similar (but not identical) ram instantiations/ state machines/ clock domain re-synch processes etc. This ends up a bit tedious and I've been wondering how to circumvent the tedium.

I've been looking at the grahical state machine entry facility of Modelsim Design and wondering if it's any good and would end up saving any time. I suspect not or the software industry would have adopred this sort of design entry method years ago.

This started me wondering what the favourite design entry optomisation methods of our experienced comp.arch.fpga contributors are? Has anyone had any success with graphical entry?

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board

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Nial Stewart
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I can't believe I spelt optimisation wrongly :-(

Nial

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Nial Stewart

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin,

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Reply to
Ray Andraka

[...]

I have to admit I'm a fan of Renoir, or "HDL Designer" as it's now called. I also prefer VHDL, despite its verbosity - I rarely see the verbosity, certainly don't have to type much of it. I can't say that graphical entry provides much optimisation, but IMO it makes visualisation, navigating and maintaining a complex hierarchy a relatively easy task.

If "Modelsim Design" is Renoir/HDL designer (block and state diagrams) packaged together with Modelsim, then it gets one vote here.

- Brian

Reply to
Brian Drummond

The downside of this approach is that you can disguise the functionality of what's going on with multiple sub-component instantiations.

I suppose it's swings and roundabouts, simpler more easily decipherable design files or a reduction in time spent on design entry.

Nial.

Reply to
Nial Stewart

Hi Nial, When Ray posted I thought he was stating the bleeding obvious; apparently not! Maybe I'm missing something, but are you saying you've been doing HDLs for 10 years and you don't have a bunch of useful entities that you reuse? I don't see how this approach disguises the functionality. They're certainly the most tested and best documented parts of my code. The hierarchy improves readability. As Ray says, when something new comes up that's close to what you did before, I add stuff so the new block does both old and new. Generics are especially useful here. Ah well, each to his own. Cheers, Syms.

Reply to
Symon

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