Re: Quartus removes Tristate Buffer

But he has said only the pin out is tri-stated.

I presume the structure is something like

pin good recommendation! lpm_bustri() function is poorly designed and

Why use primitives? Is it not easier to infer the tr-state as above? This makes device/manufacturer migration easier too.

Nial.

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

" hi data bus driver : lpm bustri GENERIC MAP (LPM WIDTH => 30) PORT MAP (

result => dnio_inbus,

dnio and dnio_inbus are internal data buses. "

I guess he tried to do something like (sorry for my syntax, i'm not a native VHDL speaker):

if (n0_dir = '1') { // enabletr = '1' dnio_inbus

ws:...

IMO the word =A8bus=A8 does not mean necesserily a tri-stated _multisourc= e_=20 data path. In my case these =A8internal data buses=A8 are NOT tri-stated = and=20 they have one single source, is the case of dnio_inbus this is the=20 lpm_tribuf.

As I mentioned above, this is not the case. No 'Z' assignment.

As I understand the VHDL lpm_tribuf will be translated to TRI primitive. =

It also happens in many of my designs. But sometimes - and this was the=20 original question - Quartus replaces the TRI buffer by an OR gate and I=20 do not know why. There is no visible reason. When I connect the input=20 and control input of such a buffer to testpoints, they change their=20 state correctly.

Thanks,

Janos Ero CERN Div. EP

Michael S (and earlier Martin Schoeberl) had written

erojr wrote:

Well I think I understand what you're both saying, so let me make a total fool of myself and put my two cents in...

You may not be directly assigning Z to any signal, but that's what you're asking for inside lpm_bustri.

------------------------------------------------------- A. Quartus II Help says:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - WOPT_MLS_SIGNALS_FEEDING_IN_LOGIC_WILL_NOT_BE_TRISTATED

CAUSE: You connected the specified logic gate to a tri-state signal (Z logic value), but you cannot create internal tri-state buffers. Therefore, if the signal feeding into the node is Z, it will become a "1" instead.

ACTION: No action is required.

------------------------------------------------------- B. Quartus II Help on LPM_BUSTRI

- - - - - - - - - - - - - - - - - - - - - - - - - - - -

The following three configurations are valid:

1. All ports are present: input ports data[LPM_WIDTH-1..0], enabledt, and enabletr; output ports result[LPM_WIDTH-1..0]; and bidirectional ports tridata[LPM_WIDTH-1..0]. This configuration has the following function:

Input Bidirectional Output enabledt enabletr tridata[LPM_WIDTH-1..0] result[LPM_WIDTH-1..0]

-------------------------------------------------------

This is the configuration that corresponds to your connections. But "result" is an internal bus, and it is not allowed to be assigned a value "Z".

So Z => 1, and (I imagine) you're getting something like:

signal dtvector : std_logic_vector(result'length-1 downto 0);

dtvector enabledt); -- vector of enabledt repeated result GENERIC MAP (LPM WIDTH => 30

It sure gets frustrating at times. Hope this helps,

-rajeev-

/snip/

Thanks, this has helped indeed. The dnio_inbus is now connected directly =

to the pin. An interesting consequence: Quartus pin assignment lists=20 show the same pins twice: once as inputs once as tri-state outputs.

There are, however, some open questions remaining.

same behavior as the Fitting tool Quartus.

Thanks for your help.

Janos Ero CERN Div. EP