> The answer is simple: You don't have tristate busses inside (Altera)
> > FPGAs. Tristate buffers are substituded by MUX.
>
> There are no tristate buses inside. The only tristate bus is directly
> connected to the pins, in the lpm definition this is the pin name. The
> internal buses have only one source, in the case of the result this
> is the tristate buffer.
>
> Thanks for the help, but this is not the case.
>
> Janos Ero
> CERN Div. EP
result port is connected to internal bus in your design.
Internal nodes (buses) can't be tristated in Altera FPGAs (AFAIK, that's true for newer Xilinx FPGAs as well). Internal nodes are '0' or '1' - no 'Z'.
I don't understand what exactly you don't understand :(
P.S. Altera recommends using TRI primitives rather than lpm_bustri(). Very good recommendation! lpm_bustri() function is poorly designed and misleading.
IMO the word =A8bus=A8 does not mean necesserily a tri-stated _multisourc= e_=20 data path. In my case these =A8internal data buses=A8 are NOT tri-stated = and=20 they have one single source, is the case of dnio_inbus this is the=20 lpm_tribuf.
As I mentioned above, this is not the case. No 'Z' assignment.
As I understand the VHDL lpm_tribuf will be translated to TRI primitive. =
It also happens in many of my designs. But sometimes - and this was the=20 original question - Quartus replaces the TRI buffer by an OR gate and I=20 do not know why. There is no visible reason. When I connect the input=20 and control input of such a buffer to testpoints, they change their=20 state correctly.
CAUSE: You connected the specified logic gate to a tri-state signal (Z logic value), but you cannot create internal tri-state buffers. Therefore, if the signal feeding into the node is Z, it will become a "1" instead.
ACTION: No action is required.
------------------------------------------------------- B. Quartus II Help on LPM_BUSTRI
All ports are present: input ports data[LPM_WIDTH-1..0], enabledt, and enabletr; output ports result[LPM_WIDTH-1..0]; and bidirectional ports tridata[LPM_WIDTH-1..0]. This configuration has the following function:
Thanks, this has helped indeed. The dnio_inbus is now connected directly =
to the pin. An interesting consequence: Quartus pin assignment lists=20 show the same pins twice: once as inputs once as tri-state outputs.
There are, however, some open questions remaining.
1./ It helped only in the given case. I have another design, where the=20 enableTR =3D> '1' and the result connection is unused (the output is=20 used as tristate output, no input) and the TRI buffer is replaced by an=20 OR gate.
2./ In both cases the compilation (Cadence) and the behavioral=20 simulation (Cadence NCsim) that uses Altera=B4s own=20 ldv40.5/altera/quartusIIv3.0/lpm/ libraries does its job without any=20 warning or error message. I guess the simulation library should show the =
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