eliminating a DDS

Ok, I got you. That's interesting. It requires the same external equipment as the traditional sine wave DDS with a DAC, analog filter and comparator except for the filter with the addition of something to zero out the integrator. The value fed to the DAC would need to be scaled to the inverse of the phase step size, a PITA in digital. That likely would be done in a look up table. This is all feasible, but I don't know how piratical to get the jitter from 10 ns down to say, 100 ps.

Then it might be a good idea to use the FPGA to double or quadruple the

AD9835 has single-ended DAC output, right? I don't see how you achieve jitter in picosecond range when you start with single-ended 20MHz signal followed by filter and comparator. Ground drift alone will put jitter into 10s of ps range, but more likely into over 100 ps.

Another problem is a input clock to AD9835 which is also single-ended and also have relatively low frequency (50 MHz). Again, ground noise would be translated into relatively high jitter. Or do you say that the all jitter *before* low-pass (or band-pass) filter is of no significance? I am not sure that it is true.

Proper PCB layout will prevent ground loop voltages. The DDS output is a current source, which helps a lot. A passive LC filter can be terminated at one end, at the comparator.

Single-ended logic signals can have fs RMS jitter. Again, ground loops should be avoided. I can put the 50 MHz XO close to the DDS, and run a long trace to the Ethernet gadget; it doesn't care much about jitter.

I don't recall saying that. But since I only need an octave clock range, a bandpass filter will reject both high and low-frequency jitter that's out of the filter's passband. At an octave bw, it's about a toss-up between an official bandpass filter and cascaded lowpass+highpass filters.

A tunable narrowband filter would be cool. It could track the DDS frequency. There are a few interesting ways to do that. But that would be work, and a brute-force long elliptical filter would be as good.

All of which is wandering off the FPGA topic.

ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz ch2, through a PLL in jitter filtermode

with an increment that results in exactly 25MHz:

-Lasse

Looks like classic DDS squirmies. The PLL is not filtering the jitter much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC lowpass filter usually looks pretty good.

A PLL, considered as a tracking bandpass filter, could potentially be a good DDS cleanup.

That's the moral equivalent of dividing 100 MHz by 4!

Thanks, interesting stuff.

Den onsdag den 7. september 2016 kl. 23.49.29 UTC+2 skrev John Larkin:

in:

et ~20MHz

maybe it's possible to have the filter and then run it back in to the FPGA and through fpga PLL? though lowest BW for the PLL is 1MHz

I tried upping the clock to 400MHz and it got quite a lot better, but I've only got a TDS210 scope here so it's hard to tell how much better

put the DDS inside the loop ?

I know, it was a sanity check ;)

-Lasse

Yeah, there is jitter cleanup, but it only lasts about 100 ns. The PLL is pretty fast.

I don't see how that can matter. The DDS will in general create jitter of one clock period in regardless of what that clock is. If the PLL doesn't filter jitter in the reference, is it likely to filter jitter in the feed back clock?

Several FPGAs contain PLLs. The PLLs in the Lattice XO2/XO3 FPGAs have a zillion dynamically programmable (Wishbone bus) parameters, including the various dividers and multiplexers, and a spiffy fractional divider in the feedback path.