dual clock fifo

I would suggest to use what I do:

Use a circular addr counter on both sides, make a signal that will indicate that its 1/4 full and reclock that single signal to the other side (edge detecting to single clock), to indicate its safe to read 1/4 of the ramblock. To give a message back to the input clock domain, create a similar signal on the read side telling that 1/4 is used, telling input tocontinue to write 1/4 more data. You could be using 1/2 size partitions too, but quads (or even smaller portions) gives you some headroom to fill more memory while reading. If you partition the ram into too small partitions, the reclocking of a filled part will not work (you do not want to loose any of these signals). You can calculate the minimum partition by comparing the clocking ration of your domains, ensuring that every 1/n'th fill will be guaranteed to reclock.

Reply to
Morten Leikvoll
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Design the entire FIFO (counters & flags logic) to run at 320MHz and add a clock domain transfer circuit on the low frequency side.

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Reply to
Nico Coesel

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