Hi all,
I am implementing the DPLL functionality of 74LS297 in an FPGA. For the K-counter in that block there are two outputs namely carry and borrow. I will just explain how i have implemented this. The phase detector(ECPD) output is fed to the K counter if it is high" the counter increments else decrements.In my implementation i have tied ABCD="1000" i.e it is 3 stages long (3 - bit counter). Now the "carry" is set high when phasedetector output is high and K counter value is "111". The "borrow" is set high when phasedetector output is low and K counter value is "000". i wanted to know if what ever i have implemented is right or if i am going wrong anywhere.
can anybody tell me how this "carry" and "borrow" signals are really used and generated.
Thanks in advance.
rgds, prav