I'm designing a debounce filter using Finite State Machine. The FSM behavior is it follows the inital input bit and thinks that's real output until it receives 3 consecutive same bits and it changes output to that 3 consecutive bit until next 3 consecutive bits are received. A reset will set the FSM to output 1s until it receives the correct input and ouput.

This is the test sequence with input and correct output.

1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input) 1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)The state diagram I came up has 6 states and it's named SEE1, SEE11, SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in the input. Because it just came from SEE1 and before SEE1, it came from SEE000, so at SEE1 it can not change ouput to 1 which is what I have specified that state's ouput to be.

Anyone knows how to solve this problem? Or maybe there's other better ways to design the state diagram?

Thanks,

Anson